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1. 发明授权

US07652321B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07652321B2
公开(公告)日：2010-01-26
申请号：US11072632
申请日：2005-03-07
申请人： Tetsuji Yamaguchi , Kiyoshi Kato
发明人： Tetsuji Yamaguchi , Kiyoshi Kato
IPC分类号： H01L29/72
CPC分类号： H01L21/84 , H01L27/11526 , H01L27/11546 , H01L27/1203
摘要： In a process of manufacturing elements of different structures and characteristics on the same substrate at the same time, the number of steps is increased and complicated. In view of this, the invention provides a semiconductor device and a manufacturing process thereof in which elements of different structures are formed on the same substrate while reducing the number of steps. According to the invention, in accordance with a memory transistor that requires the largest number of steps when being formed among elements that forms a semiconductor memory device, other high speed transistor and high voltage transistor are efficiently manufactured. Thus, the number of steps is suppressed and a low cost semiconductor memory device can be manufactured.
摘要翻译：在同一基板上同时制造不同结构和特性的元件的过程中，台阶增加复杂。鉴于此，本发明提供了一种半导体器件及其制造方法，其中不同结构的元件形成在同一衬底上，同时减少了步骤数。根据本发明，根据在形成半导体存储器件的元件之间形成最大数量的步骤的存储晶体管时，有效地制造其它高速晶体管和高压晶体管。因此，抑制了步数，并且可以制造低成本的半导体存储器件。

2. 发明申请

US20080211024A1 Memory Device and Manufacturing Method of the Same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080211024A1
公开(公告)日：2008-09-04
申请号：US10573527
申请日：2005-05-31
申请人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
发明人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/1203
摘要： An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.
摘要翻译：提供易于使用和便宜的存储器件，同时在与其它功能电路形成在同一衬底上的存储器的同时保持产品规格和生产率。本发明的存储器件包括形成在绝缘表面上的存储单元。存储单元包括具有两个杂质区域的半导体膜，栅极电极和连接到各个杂质区域的两个布线。通过在栅电极和两条布线中的至少一个之间施加电压来改变半导体膜的状态，两个布线彼此绝缘。

3. 发明申请

US20050194645A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050194645A1
公开(公告)日：2005-09-08
申请号：US11072632
申请日：2005-03-07
申请人： Tetsuji Yamaguchi , Kiyoshi Kato
发明人： Tetsuji Yamaguchi , Kiyoshi Kato
IPC分类号： H01L27/115 , H01L29/10
CPC分类号： H01L21/84 , H01L27/11526 , H01L27/11546 , H01L27/1203
摘要： In a process of manufacturing elements of different structures and characteristics on the same substrate at the same time, the number of steps is increased and complicated. In view of this, the invention provides a semiconductor device and a manufacturing process thereof in which elements of different structures are formed on the same substrate while reducing the number of steps. According to the invention, in accordance with a memory transistor that requires the largest number of steps when being formed among elements that forms a semiconductor memory device, other high speed transistor and high voltage transistor are efficiently manufactured. Thus, the number of steps is suppressed and a low cost semiconductor memory device can be manufactured.
摘要翻译：在同一基板上同时制造不同结构和特性的元件的过程中，台阶增加复杂。鉴于此，本发明提供了一种半导体器件及其制造方法，其中不同结构的元件形成在同一衬底上，同时减少了步骤数。根据本发明，根据在形成半导体存储器件的元件之间形成最大数量的步骤的存储晶体管时，有效地制造其它高速晶体管和高压晶体管。因此，抑制了步数，并且可以制造低成本的半导体存储器件。

4. 发明授权

US08114719B2 Memory device and manufacturing method of the same 有权
标题翻译：存储器件及其制造方法相同
公开(公告)号：US08114719B2
公开(公告)日：2012-02-14
申请号：US10573527
申请日：2005-05-31
申请人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
发明人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/1203
摘要： An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.
摘要翻译：提供易于使用和便宜的存储器件，同时在与其它功能电路形成在同一衬底上的存储器的同时保持产品规格和生产率。本发明的存储器件包括形成在绝缘表面上的存储单元。存储单元包括具有两个杂质区域的半导体膜，栅极电极和连接到各个杂质区域的两个布线。通过在栅电极和两条布线中的至少一个之间施加电压来改变半导体膜的状态，两个布线彼此绝缘。

5. 发明申请

US20160274965A1 SYSTEM OPERATIONS MANAGEMENT APPARATUS, SYSTEM OPERATIONS MANAGEMENT METHOD AND PROGRAM STORAGE MEDIUM 审中-公开
公开(公告)号：US20160274965A1
公开(公告)日：2016-09-22
申请号：US15166485
申请日：2016-05-27
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0709 , G06F11/0751 , G06F11/0787 , G06F11/3452 , G06Q10/02
摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

6. 发明授权

US09384079B2 System operations management apparatus, system operations management method and program storage medium 有权
公开(公告)号：US09384079B2
公开(公告)日：2016-07-05
申请号：US14589255
申请日：2015-01-05
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06F11/00 , G06F11/07 , G06Q10/02 , G06F11/34
CPC分类号： G06F11/079 , G06F11/0709 , G06F11/0751 , G06F11/0787 , G06F11/3452 , G06Q10/02
摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

7. 发明授权

US09188631B2 Element substrate, inspecting method, and manufacturing method of semiconductor device 有权
标题翻译：元件基板，检查方法和半导体器件的制造方法
公开(公告)号：US09188631B2
公开(公告)日：2015-11-17
申请号：US13446614
申请日：2012-04-13
申请人： Kiyoshi Kato , Konami Izumi , Masahiko Hayakawa , Koichiro Kamata
发明人： Kiyoshi Kato , Konami Izumi , Masahiko Hayakawa , Koichiro Kamata
IPC分类号： G01R31/02 , G01R31/28 , G01R31/302 , H01L27/13
CPC分类号： G01R31/2822 , G01R31/2886 , G01R31/3025 , H01L27/13
摘要： A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit.
摘要翻译：提供了包括可以以高可靠性评估元件的特性的半导体层的基板及其评价方法。包括本发明的半导体层的衬底具有一个闭环电路，其中天线线圈和半导体元件串联连接，并且形成有电路的区域的表面被绝缘膜覆盖。通过使用这样的电路，可以进行非接触检查。此外，环形振荡器可以代替闭环电路。

8. 发明授权

US08946710B2 Semiconductor device and electronic apparatus using the same 有权
标题翻译：半导体装置及使用其的电子设备
公开(公告)号：US08946710B2
公开(公告)日：2015-02-03
申请号：US13358554
申请日：2012-01-26
申请人： Kiyoshi Kato , Takeshi Osada
发明人： Kiyoshi Kato , Takeshi Osada
IPC分类号： H01L29/04 , H01L27/13 , H03K3/03 , H03K5/13 , H03K23/58 , H03L7/085 , H03L7/099 , H03L7/18 , H01L27/12 , H03K5/00
CPC分类号： H01L27/13 , H01L27/1214 , H01L27/1266 , H03K3/0315 , H03K5/133 , H03K23/582 , H03K2005/00039 , H03K2005/00202 , H03L7/085 , H03L7/0995 , H03L7/18
摘要： A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved.
摘要翻译：具有功能高，功能多，附加值高的半导体器件。半导体器件包括提供在衬底上并且输出具有正确频率的信号的PLL电路。通过在衬底上设置这样的PLL电路，可以实现具有高功能，多功能和高附加值的半导体器件。

9. 发明授权

US08896046B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08896046B2
公开(公告)日：2014-11-25
申请号：US13285450
申请日：2011-10-31
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： H01L27/108 , H01L27/105 , H01L27/115 , H01L27/06 , H01L27/12
CPC分类号： H01L27/108 , H01L27/0688 , H01L27/105 , H01L27/11551 , H01L27/1156 , H01L27/1225 , H01L27/124 , H01L29/7869
摘要： Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.
摘要翻译：提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入次数没有限制。半导体器件包括包括氧化物半导体（在更广泛的意义上是截止电流足够小的晶体管）的晶体管的存储器电路和包括晶体管的诸如驱动器电路的外围电路，该晶体管包括除了氧化物半导体（即，能够以足够高的速度运行的晶体管）。此外，外围电路设置在下部，并且存储电路设置在上部，使得可以减小半导体器件的面积和尺寸。

10. 发明授权

US08779433B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08779433B2
公开(公告)日：2014-07-15
申请号：US13115239
申请日：2011-05-25
申请人： Atsuo Isobe , Yoshinori Ieda , Kiyoshi Kato , Yuto Yakubo , Yuki Hata
发明人： Atsuo Isobe , Yoshinori Ieda , Kiyoshi Kato , Yuto Yakubo , Yuki Hata
IPC分类号： H01L29/10 , H01L27/115 , H01L27/108
CPC分类号： H01L27/10852 , G11C16/0433 , H01L27/11521 , H01L27/1156 , H01L27/1225
摘要： It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.
摘要翻译：本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入数量没有限制。半导体器件包括设置在第一晶体管上的第二晶体管和电容器。使用具有相对于栅电极的蚀刻选择性的材料形成与第一晶体管的栅电极接触的第二晶体管的源电极。通过使用相对于第一晶体管的栅电极具有蚀刻选择性的材料形成第二晶体管的源电极，可以减小布局的裕度，从而可以提高半导体器件的集成度。

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