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1. 发明申请

US20080211024A1 Memory Device and Manufacturing Method of the Same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080211024A1
公开(公告)日：2008-09-04
申请号：US10573527
申请日：2005-05-31
申请人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
发明人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/1203
摘要： An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.
摘要翻译：提供易于使用和便宜的存储器件，同时在与其它功能电路形成在同一衬底上的存储器的同时保持产品规格和生产率。本发明的存储器件包括形成在绝缘表面上的存储单元。存储单元包括具有两个杂质区域的半导体膜，栅极电极和连接到各个杂质区域的两个布线。通过在栅电极和两条布线中的至少一个之间施加电压来改变半导体膜的状态，两个布线彼此绝缘。

2. 发明授权

US08114719B2 Memory device and manufacturing method of the same 有权
标题翻译：存储器件及其制造方法相同
公开(公告)号：US08114719B2
公开(公告)日：2012-02-14
申请号：US10573527
申请日：2005-05-31
申请人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
发明人： Kiyoshi Kato , Tetsuji Yamaguchi , Etsuko Asano , Konami Izumi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/1203
摘要： An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.
摘要翻译：提供易于使用和便宜的存储器件，同时在与其它功能电路形成在同一衬底上的存储器的同时保持产品规格和生产率。本发明的存储器件包括形成在绝缘表面上的存储单元。存储单元包括具有两个杂质区域的半导体膜，栅极电极和连接到各个杂质区域的两个布线。通过在栅电极和两条布线中的至少一个之间施加电压来改变半导体膜的状态，两个布线彼此绝缘。

3. 发明申请

US20050250308A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050250308A1
公开(公告)日：2005-11-10
申请号：US11121110
申请日：2005-05-04
申请人： Tetsuji Yamaguchi , Etsuko Asano , Naomi Yazaki , Tomoya Futamura , Tomoko Nishikawa
发明人： Tetsuji Yamaguchi , Etsuko Asano , Naomi Yazaki , Tomoya Futamura , Tomoko Nishikawa
IPC分类号： H01L21/77 , H01L21/84 , H01L31/20
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/78621
摘要： The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to plasma during dry etching are not generated in a semiconductor layer. Accordingly, it is an object of the invention to provide a method not for generating the deterioration of the transistor characteristic especially in a thin film transistor having a minute structure.
摘要翻译：本发明提供一种具有高特性和可靠性的半导体器件的制造方法。防止在绝缘膜上形成电极或布线之后的干蚀刻期间的蚀刻损伤。通过形成导电层来抑制损伤，使得在半导体层中不产生由干蚀刻期间的等离子体引起的带电粒子。因此，本发明的目的是提供一种不产生晶体管特性劣化的方法，特别是在具有微小结构的薄膜晶体管中。

4. 发明授权

US07521368B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07521368B2
公开(公告)日：2009-04-21
申请号：US11121110
申请日：2005-05-04
申请人： Tetsuji Yamaguchi , Etsuko Asano , Naomi Yazaki , Tomoya Futamura , Tomoko Nishikawa
发明人： Tetsuji Yamaguchi , Etsuko Asano , Naomi Yazaki , Tomoya Futamura , Tomoko Nishikawa
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/78621
摘要： The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to plasma during dry etching are not generated in a semiconductor layer. Accordingly, it is an object of the invention to provide a method not for generating the deterioration of the transistor characteristic especially in a thin film transistor having a minute structure.
摘要翻译：本发明提供一种具有高特性和可靠性的半导体器件的制造方法。防止在绝缘膜上形成电极或布线之后的干蚀刻期间的蚀刻损伤。通过形成导电层来抑制损伤，使得在半导体层中不产生由干蚀刻期间的等离子体引起的带电粒子。因此，本发明的目的是提供一种不产生晶体管特性劣化的方法，特别是在具有微小结构的薄膜晶体管中。

5. 发明申请

US20070228371A1 Method for Evaluating Semiconductor Device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US20070228371A1
公开(公告)日：2007-10-04
申请号：US11758066
申请日：2007-06-05
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： H01L23/58
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

6. 发明申请

US20050273290A1 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US20050273290A1
公开(公告)日：2005-12-08
申请号：US11132434
申请日：2005-05-19
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： G01R31/317 , G01R31/3187 , G06F19/00
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

7. 发明授权

US07567882B2 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US07567882B2
公开(公告)日：2009-07-28
申请号：US11758066
申请日：2007-06-05
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： G01R31/00 , G01R31/26
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

8. 发明授权

US07231310B2 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US07231310B2
公开(公告)日：2007-06-12
申请号：US11132434
申请日：2005-05-19
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： G06F19/00
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

9. 发明授权

US07202149B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07202149B2
公开(公告)日：2007-04-10
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

10. 发明授权

US08822272B2 Semiconductor device, manufacturing method thereof, and measuring method thereof 有权
标题翻译：半导体装置及其制造方法及其测定方法
公开(公告)号：US08822272B2
公开(公告)日：2014-09-02
申请号：US11885958
申请日：2006-03-17
申请人： Takuya Tsurume , Etsuko Asano
发明人： Takuya Tsurume , Etsuko Asano
IPC分类号： H01L29/36
CPC分类号： G01R31/2601 , G01R31/2607 , G01R31/2822 , G01R31/2884 , H01L21/6835 , H01L21/78 , H01L22/14 , H01L22/34 , H01L23/66 , H01L2221/68359 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.
摘要翻译：提供能够容易进行物理测试而不劣化特性的半导体器件。根据半导体器件的测量方法，其中设置有包括端子部分的测试元件的元件层被具有柔性的第一和第二膜密封，去除在端子部分上形成的第一膜以形成到达端子部分接触孔填充含有导电材料的树脂; 在将具有柔性的布线基板布置在已经进行了填充的树脂上之后进行加热，使得具有柔性的端子部分和布线基板通过包含导电材料的树脂电连接; 并进行测量。

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