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1. 发明授权

US5248378A Method and apparatus for producing silicon single crystal 失效
标题翻译：生产硅单晶的方法和装置
公开(公告)号：US5248378A
公开(公告)日：1993-09-28
申请号：US852612
申请日：1992-03-17
申请人： Tetsuhiro Oda , Izumi Fusegawa , Hirotoshi Yamagishi , Atsushi Iwasaki , Akiho Maeda , Shinobu Takeyasu , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Tetsuhiro Oda , Izumi Fusegawa , Hirotoshi Yamagishi , Atsushi Iwasaki , Akiho Maeda , Shinobu Takeyasu , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： C30B15/00 , C30B15/14 , C30B29/06
CPC分类号： C30B29/06 , C30B15/14 , Y10S117/90 , Y10T117/1068
摘要： A method of producing a Czochralski-grown silicon single crystal stably and efficiently with high production yield comprises the steps of setting pulling conditions such that at least a portion of a growing silicon single crystal having a temperature in excess of 1150.degree. C. is spaced upwardly from a surface of silicon melt by a distance greater than 280 mm; and pulling the growing silicon single crystal upward while maintaining the pulling conditions. The silicon single crystal produced by this method has an excellent oxide film dielectric breakdown strength. An apparatus for carrying out the method is also disclosed.

2. 发明授权

US5386796A Method for testing quality of silicon wafer 失效
标题翻译：测试硅片质量的方法
公开(公告)号：US5386796A
公开(公告)日：1995-02-07
申请号：US850916
申请日：1992-03-13
申请人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： C30B33/10 , C30B29/06 , C30B33/00 , C30B15/00
CPC分类号： C30B29/06 , C30B33/00
摘要： Quick and inexpensive determination of an aggregate of point defects in a grown silicon semiconductor single crystal bar is accomplished by a method which comprises cutting a wafer from a freshly grown silicon single crystal bar, etching the surface of this wafer with the mixture of hydrofluoric acid and nitric acid thereby relieving the wafer of strain, treating the wafer with the mixture of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid, and water thereby giving rise to pits 2 and ripple patterns 1 therein, determining the density of the pits 2 and that of the ripple patterns 1, and rating the aggregate of point defects by virtue of the correlation between the densities of the pits 1 and the ripple patterns 1 and the aggregate of point defects.
摘要翻译：在生长的硅半导体单晶棒中快速且廉价地测定点缺陷的集合是通过一种方法实现的，该方法包括从新生成的硅单晶棒切割晶片，用氢氟酸和硝酸，从而减轻晶片的应变，用K2Cr2O7，氢氟酸和水的混合物处理晶片，从而在其中产生凹坑2和波纹图案1，确定凹坑2的密度和波纹图案1的密度，并且通过凹坑1的密度与波纹图案1和点缺陷的总和之间的相关性对点缺陷的总和进行评级。

3. 发明授权

US5262338A Method for fabrication of semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5262338A
公开(公告)日：1993-11-16
申请号：US850506
申请日：1992-03-13
申请人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： H01L21/02 , H01L21/28 , H01L21/322 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28211 , H01L21/3225
摘要： A semiconductor device of the MOS construction such that a gate oxide film of the device has a gate area in the range of from 5 to 15 mm.sup.2 and a thickness in the range of from 15 to 40 nm and the oxide film dielectric breakdown voltage is not less than 8 MV/cm when a gate current caused to flow in response to application of a direct-current voltage between a phosphorus-doped polysilicon electrode formed on the oxide film and a silicon single crystal substrate increases past 1 .mu.A/mm.sup.2 as current density is obtained by using a silicon wafer substrate having an oxygen concentration of not more than 1.times.10.sup.18 atoms/cm.sup.3.

4. 发明授权

US5688319A Method for testing electrical properties of silicon single crystal 失效
标题翻译：测试硅单晶电性能的方法
公开(公告)号：US5688319A
公开(公告)日：1997-11-18
申请号：US796385
申请日：1991-11-22
申请人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： H01L21/66 , G01N27/92 , G01R31/26 , G01R31/28 , C30B15/00
CPC分类号： G01N27/92 , G01R31/2831 , Y10S148/06 , Y10S148/162
摘要： The evaluation of the oxide film dielectric breakdown voltage of a silicon semiconductor single crystal is caried out by cutting a wafer out of the single crystal rod, etching the surface of the wafer with the mixed solution of hydrofluoric acid and nitric acid thereby relieving the wafer of strain, then etching the surface of the wafer with the mixed solution of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid, and water therby inducing occurrence of pits and scale-like patterns on the surface, determining the density of the scale-like patterns, and computing the oxide film dielectric breakdown voltage by making use of the correlating between the density of scale-like patterns and the oxide film dielectric breakdown voltage. This fact established the method of this invention to be capable of effecting an evaluation equivalent to the evaluation of the oxide film dielectric breakdown voltage of a PW wafer prepared from the single crystal rod.
摘要翻译：通过从单晶棒切割晶片，对硅半导体单晶的氧化膜介电击穿电压进行评估，用氢氟酸和硝酸的混合溶液蚀刻晶片的表面，从而使晶片然后用K2Cr2O7，氢氟酸和水的混合溶液蚀刻晶片表面，从而在表面上引起凹坑和鳞片状图案的发生，确定鳞片状图案的密度，并计算氧化膜通过利用鳞片状图案的密度与氧化膜介质击穿电压之间的相关性，介电击穿电压。这一事实确定了本发明的方法能够进行与从单晶棒制备的PW晶片的氧化膜介电击穿电压的评估相当的评估。

5. 发明授权

US5834322A Heat treatment of Si single crystal 失效
标题翻译： Si单晶热处理
公开(公告)号：US5834322A
公开(公告)日：1998-11-10
申请号：US916291
申请日：1997-08-22
申请人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： C30B33/02 , C30B15/00 , C30B29/06 , C30B33/00 , H01L21/322
CPC分类号： C30B15/00 , C30B29/06 , C30B33/00 , C30B33/02 , H01L21/3225
摘要： The method of this invention for heat treatment of a Si single crystal grown by the Czochralski method at a speed of pull of not less than 0.8 mm/min., characterized by heat-treating at a temperature in the range of from 1,150.degree. C. to 1,280.degree. C. a wafer cut out of the Si single crystal thereby producing a Si wafer excellent in oxide film dielectric breakdown voltage characteristic due to elimination of crystal defects. Consequently, this invention ensures production of LSI in a high yield.
摘要翻译：本发明的热处理方法，用于以不低于0.8mm /分钟的拉伸速度通过切克劳斯基法生长的Si单晶进行热处理，其特征在于在1150℃的温度下进行热处理。从Si单晶切出的晶片，由此产生由于消除晶体缺陷而具有优异的氧化膜介电击穿电压特性的Si晶片。因此，本发明能够高效率地制造LSI。

6. 发明授权

US5534112A Method for testing electrical properties of silicon single crystal 失效
标题翻译：测试硅单晶电性能的方法
公开(公告)号：US5534112A
公开(公告)日：1996-07-09
申请号：US238722
申请日：1994-05-05
申请人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
发明人： Izumi Fusegawa , Hirotoshi Yamagishi , Nobuyoshi Fujimaki , Yukio Karasawa
IPC分类号： H01L21/66 , G01N27/92 , G01R31/26 , G01R31/28 , H01L21/306
CPC分类号： G01N27/92 , G01R31/2831 , Y10S148/06 , Y10S148/162
摘要： The evaluation of the oxide film dielectric breakdown voltage of a silicon semiconductor single crystal is caried out by cutting a wafer out of the single crystal rod, etching the surface of the wafer with the mixed solution of hydrofluoric acid and nitric acid thereby relieving the wafer of strain, then etching the surface of the wafer with the mixed solution of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid, and water thereby inducing occurrence of pits and scale-like patterns on the surface, determining the density of the scale-like patterns, and computing the oxide film dielectric breakdown voltage by making use of the correlating between the density of scale-like patterns and the oxide film dielectric breakdown voltage. This fact established the method of this invention to be capable of effecting an evaluation equivalent to the evaluation of the oxide film dielectric breakdown voltage of a PW wafer prepared from the single crystal rod.
摘要翻译：通过从单晶棒切割晶片，对硅半导体单晶的氧化膜介电击穿电压进行评估，用氢氟酸和硝酸的混合溶液蚀刻晶片的表面，从而使晶片然后用K2Cr2O7，氢氟酸和水的混合溶液蚀刻晶片的表面，从而在表面上引起凹坑和鳞片状图案的发生，确定鳞片状图案的密度，并计算氧化膜通过利用鳞片状图案的密度与氧化膜介质击穿电压之间的相关性，介电击穿电压。这一事实确定了本发明的方法能够进行与从单晶棒制备的PW晶片的氧化膜介电击穿电压的评估相当的评估。

7. 发明授权

US5464779A Method and apparatus for evaluation of semiconductor production process 失效
标题翻译：用于半导体生产过程评估的方法和装置
公开(公告)号：US5464779A
公开(公告)日：1995-11-07
申请号：US223053
申请日：1994-04-05
申请人： Nobuyoshi Fujimaki
发明人： Nobuyoshi Fujimaki
IPC分类号： G01N21/88 , G01N21/47 , G01N21/84 , G01N21/94 , G01N21/95 , G01N21/956 , G01N27/72 , H01L21/66
CPC分类号： G01N21/9501 , G01N21/9503 , G01N2021/8461 , G01N21/47 , H01L22/12 , Y10S148/162
摘要： The method and apparatus of this invention for evaluation of a semiconductor production process effect the determination of the shallow pit density of a silicon wafer by predetermining the correlation between the average shallow pit density on a wafer surface obtained by microscopic observation and the average magnitude of a scattered light on the wafer surface obtained by the determination with the wafer surface inspection system operated in the haze mode, determining the average magnitude on the wafer surface of a scattered light for a silicon wafer treated by a semiconductor production process under evaluation, and analyzing the data found by the determination in combination with the correlation mentioned above. Thus, they bring about an effect of enabling the determination to be carried out automatically and quickly and exalting the accuracy of determination and allowing a generous cut in the time required for the determination as compared with the conventional determination resorting to visual measurement and evaluation.
摘要翻译：用于评估半导体制造工艺的本发明的方法和装置通过预先确定通过显微镜观察获得的晶片表面上的平均浅坑密度与平均微孔密度之间的相关性来影响硅晶片的浅坑密度的确定通过利用在雾度模式下工作的晶片表面检查系统的确定获得的晶片表面上的散射光，确定通过评估的半导体制造工艺处理的硅晶片的散射光的晶片表面上的平均幅度，并分析通过与上述相关性的决定结合发现的数据。因此，与通过视觉测量和评估的传统判定相比，它们产生了使得能够自动且快速地进行确定的效果，并且提高了确定的准确性并且允许大量裁减所需的时间。

8. 发明授权

US5701088A Method of evaluating a MIS-type semiconductor device 失效
标题翻译：评估MIS型半导体器件的方法
公开(公告)号：US5701088A
公开(公告)日：1997-12-23
申请号：US534460
申请日：1995-09-27
申请人： Nobuyoshi Fujimaki
发明人： Nobuyoshi Fujimaki
IPC分类号： G01R31/26 , G01R31/28 , H01L21/336 , H01L21/66 , H01L29/78 , G01R31/00 , H01L21/00
CPC分类号： G01R31/2831 , G01R31/2648 , H01L22/14
摘要： A method of evaluating a MIS-type semiconductor device which comprises an insulative layer(s) and a conductive layer (s) formed one after another on a semiconductor substrate wherein: using a sample with an interface trapped charge density of 1.times.10.sup.10 /cm.sup.2 .multidot.eV or less and a mobile ionic charge density of 3.times.10.sup.10 /cm.sup.2 or less in said insulative layer, said MIS-type semiconductor device is treated by applying a positive or negative voltage in the range of 1-5 MV/cm between said semiconductor substrate and said conductive layer at a temperature of 100.degree.-300.degree. C. and maintaining this voltage for 1-60 minutes (hereafter referred to as "BT treatment"); before and after said BT treatment, the capacitance-voltage characteristics (hereafter referred to as "C-V characteristics) of said MIS-type semiconductor device are measured at room temperature; and the carrier trap density of said insulative layer is determined based on the shift of the flat band voltage of said C-V characteristics from before to after said BT treatment.
摘要翻译：一种评估MIS半导体器件的方法，其包括在半导体衬底上依次形成的绝缘层和导电层，其中：使用界面俘获电荷密度为1×10 10 / cm 2×V e以下的样品并且在所述绝缘层中的移动离子电荷密度为3×10 10 / cm 2或更小，所述MIS型半导体器件通过在所述半导体衬底和所述导电层之间施加1-5MV / cm 2范围内的正或负电压在100〜300℃的温度下保持该电压1-60分钟（以下称为“BT处理”）; 在所述BT处理之前和之后，在室温下测量所述MIS型半导体器件的电容 - 电压特性（以下称为“CV特性”），并且所述绝缘层的载流子阱密度基于所述CV特性从所述BT处理之前到之后的平带电压。

9. 发明授权

US5602061A Process and apparatus for manufacturing MOS device 失效
标题翻译：用于制造MOS器件的工艺和设备
公开(公告)号：US5602061A
公开(公告)日：1997-02-11
申请号：US167031
申请日：1993-12-16
申请人： Nobuyoshi Fujimaki
发明人： Nobuyoshi Fujimaki
IPC分类号： H01L21/316 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , Y10S438/909 , Y10S438/935
摘要： A process and apparatus for manufacturing MOS devices are disclosed. The process comprises the step of controlling a first clearance linear speeds (1st CLSs) X which is the flows of an oxidizing and an annealing gases defined as ratios of the flow rates thereof to the area of a clearance between a semiconductor wafer and the interior surface of the tube of a heat treating furnace to be at least 30 cm/min while the semiconductor wafer is oxidized and annealed. The process comprises the step of controlling a second clearance linear speed (2nd CLS) Y which is a flow of the annealing gas defined as a ratio of the flow rate thereof to the area of the clearance to be at least 100 cm/min while the semiconductor wafer is taken out of the tube. The process comprises the step of controlling a relation between the 1st CLSs X and the 2nd CLS Y so that Y.gtoreq.-2.5 X+275. The process and the apparatus reduce and control the fixed-charge density in the oxide film of a MOS device with a high repeatability.
摘要翻译：公开了一种用于制造MOS器件的工艺和装置。该方法包括控制作为氧化和退火气体的流动的第一间隙线速度（第一CLS）X的步骤，其定义为其流量与半导体晶片和内表面之间的间隙的面积的比率的热处理炉的管子至少为30cm / min，同时半导体晶片被氧化和退火。该方法包括控制第二间隙线速度（第二CLS）Y的步骤，该第二间隙线速度是作为其流量与间隙的面积的比率定义为至少100cm / min的退火气体的流量，而将半导体晶片从管中取出。该处理包括控制第一CLS X和第二CLS Y之间的关系的步骤，使得Y> = = 2.5X + 275。该方法和装置降低并控制具有高重复性的MOS器件的氧化膜中的固定电荷密度。

10. 发明授权

US5823351A Semiconductor crystal packaging device 失效
标题翻译：半导体晶体封装器件
公开(公告)号：US5823351A
公开(公告)日：1998-10-20
申请号：US617804
申请日：1996-03-07
申请人： Shinichi Matsuo , Nobuyoshi Fujimaki , Shiroyasu Watanabe , Kintaro Kato
发明人： Shinichi Matsuo , Nobuyoshi Fujimaki , Shiroyasu Watanabe , Kintaro Kato
IPC分类号： B65D21/02 , B65D85/90 , H01L21/673 , H01L21/68 , B65D85/86
CPC分类号： H01L21/67366 , B65D11/188 , B65D21/0234 , H01L21/67379 , H01L21/67386
摘要： A pair of box-like device halves are molded from polyethylene terephthalate or like elastic material. Each device half has a horizontal edge wall having a protuberance and a recess, and also raised guides and recessed guides, and it also has a downwardly convex semiconductor accommodation wall formed between its opposite side walls for accommodating semiconductor crystal. The device half further has legs extending to a greater extent than the arcuate sectional profile outer surface of the semiconductor accommodation wall. Semiconductor crystal is set in one of the device halves, which is then covered by the other device half such that the raised guides and recessed guides of the two device halves engage one another and that the protuberances and recesses engage one another. The semiconductor crystal is thus accommodated in the device halves such that it is pushed by the elastic forces of the semiconductor accommodation walls.
摘要翻译： PCT No.PCT / JP95 / 01357 Sec。 371日期：1996年3月7日 102（e）1996年3月7日PCT PCT 1995年7月7日PCT公布。公开号WO96 / 02069 日期1996年1月25日一对盒状半成品由聚对苯二甲酸乙二醇酯或类似弹性材料成型。每个装置一半具有水平边缘壁，其具有突起和凹部，并且还引导引导件和凹入引导件，并且还具有形成在其相对侧壁之间的用于容纳半导体晶体的向下凸出的半导体容纳壁。该装置还具有比半导体容纳壁的弧形截面轮廓外表面更大程度地延伸的腿。半导体晶体被设置在其中一个器件半部中，然后被另一个器件半部覆盖，使得两个器件半部的升高的引导件和凹入引导件彼此接合，并且突出部和凹部彼此接合。因此，半导体晶体被容纳在器件半部中，使得其被半导体容纳壁的弹性力推动。

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