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1. 发明授权

US4723224A Content addressable memory having field masking 失效
标题翻译：内容可寻址存储器，具有场屏蔽
公开(公告)号：US4723224A
公开(公告)日：1988-02-02
申请号：US815610
申请日：1986-01-02
申请人： Terry Van Hulett , Jesse R. Wilson , Ralph McGarity
发明人： Terry Van Hulett , Jesse R. Wilson , Ralph McGarity
IPC分类号： G06F17/30 , G11C15/04 , G11C15/00
CPC分类号： G06F17/30982 , G11C15/04
摘要： A content addressable memory (CAM) comprising a plurality of CAM cells, each including a static read/write memory (RWM) cell and an EXCLUSIVE OR (XOR) gate which couples a sense line to a ground line only if the logic state of the operand bit stored in the RWM cell does not match the logic state of an operand bit presented to the CAM cell. By arranging a selected subset of the CAM cells so that the XOR gates thereof act upon a first portion of either the sense line or the ground line while the balance of the CAM cells are arranged so that the XOR gates thereof act upon a second portion of that same line, a single coupler interposed between the first and second portions can be selectively disabled by a mask signal to simultaneously mask all of the bits stored in the subset of CAM cells during the matching operation of the CAM. If appropriate, the mask signal may comprise the bit stored in a particular one of the CAM cells.
摘要翻译：一种内容可寻址存储器（CAM），包括多个CAM单元，每个单元包括静态读/写存储器（RWM）单元和唯一或（异或）门，其仅在所述CAM单元的逻辑状态存储在RWM单元中的操作数位与呈现给CAM单元的操作数位的逻辑状态不匹配。通过布置CAM单元的所选择的子集，使得其XOR门作用在感测线或接地线的第一部分上，同时CAM单元的平衡被布置成使其XOR门作用在第二部分插入在第一和第二部分之间的单个耦合器可以被掩模信号选择性地禁用，以在CAM的匹配操作期间同时掩蔽存储在CAM单元的子集中的所有位。如果适当，掩码信号可以包括存储在特定的一个CAM单元中的位。

2. 发明授权

US5572535A Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design 失效
标题翻译：用于在电路设计中验证三态多路复用器的正确操作的方法和数据处理系统
公开(公告)号：US5572535A
公开(公告)日：1996-11-05
申请号：US270601
申请日：1994-07-05
申请人： Carl Pixley , Hyunwoo Cho , Bernard F. Plessier , Jesse R. Wilson , Ralph McGarity
发明人： Carl Pixley , Hyunwoo Cho , Bernard F. Plessier , Jesse R. Wilson , Ralph McGarity
IPC分类号： G01R31/3181 , G01R31/3183 , G01R31/3185 , H04J3/04 , G06F11/34 , G11C29/00
CPC分类号： G01R31/318371 , G01R31/3181 , G01R31/318502 , H04J3/047
摘要： A method (FIGS. 12-16) and a data processing system (FIG. 4) are used to verify the correct operation of one or more tri-state multiplexers (FIG. 3) located in a circuit model (37). The tri-state multiplexer checker (38) accesses the circuit model (37) and identifies the tri-state multiplexer(s). Once identified these tri-state multiplexers are checked to ensure that: (1) no two or more select/control lines to a tri-state MUX are enabled at a critical point in time wherein tri-state MUX output line contention can occur (i.e. both a logic zero and a logic one are being driven to the MUX output); and (2) that at least one select/control line is enabled during all critical periods of time so that a high impedance (high-Z) state is not propagated incorrectly through the MUX. This checking/verification is performed in a cut-set manner which is iterative and very time efficient when compared to prior methods.
摘要翻译：使用方法（图12-16）和数据处理系统（图4）来验证位于电路模型（37）中的一个或多个三态多路复用器（图3）的正确操作。三态复用器检测器（38）访问电路模型（37）并识别三态多路复用器。一旦确定了这些三态多路复用器被检查以确保：（1）在三态MUX输出线争用可能发生的临界时间点，三态MUX的两个或多个选择/控制线路不能被使能（即，逻辑0和逻辑1都被驱动到MUX输出）; 和（2）在所有关键时段期间至少有一个选择/控制线被使能，使得高阻抗（高Z）状态不会通过MUX错误传播。与现有方法相比，该检查/验证以切割方式执行，其是迭代且非常时间有效的。

3. 发明授权

US5029072A Lock warning mechanism for a cache 失效
标题翻译：锁定缓存的警告机制
公开(公告)号：US5029072A
公开(公告)日：1991-07-02
申请号：US144638
申请日：1988-01-11
申请人： William C. Moyer , Ralph McGarity , James G. Gay , Jesse R. Wilson
发明人： William C. Moyer , Ralph McGarity , James G. Gay , Jesse R. Wilson
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed using translation tables in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in the translation tables in association with the translation descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.
摘要翻译：在数据处理系统中，分页存储器管理单元（PMMU）使用由存储器中的翻译表构造的翻译器将处理器提供的逻辑地址转换为存储器中的物理地址。 PMMU在翻译缓存中维护一组最近使用的翻译器。响应于与特定页面的翻译描述符相关联的转换表中包含的特定锁定值，PMMU在与对应的翻译器相关联的翻译器缓存中设置锁定指示符，以排除在翻译器高速缓存中替换该翻译器。只要高速缓存中的预定数量的转换器都被锁定，锁定警告机制就会提供锁定警告信号。作为响应，PMMU可以警告处理器翻译器缓存有变得充满锁定的翻译器的危险。优选地，PMMU也被禁止锁定高速缓存中的最后一个转换器。

4. 发明授权

US06266807B1 Method and system for executing instructions in an application-specific microprocessor 失效
标题翻译：用于在特定于应用程序的微处理器中执行指令的方法和系统
公开(公告)号：US06266807B1
公开(公告)日：2001-07-24
申请号：US09150218
申请日：1998-09-09
申请人： Ralph McGarity , Franz Steininger , Jean Casteres
发明人： Ralph McGarity , Franz Steininger , Jean Casteres
IPC分类号： G06F945
CPC分类号： G06F8/447
摘要： A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are compiled into DSP-like instructions in the machine language for execution on the processor. The microcontroller-like instructions are combined with the DSP-like instructions to produce a program, the program having a virtual language portion and a machine language portion respectively. When the program is executed, the virtual language portion of the program is translated into machine language instructions, and the machine language portion of the program is directly executed, such that the application-specific microprocessor executes both the DSP-like instructions and the microcontroller-like instructions.
摘要翻译：描述用于在具有机器语言的应用特定微处理器上执行指令的方法。虚拟语言中提供了类似微控制器的指令，用于在处理器上执行。高级DSP类功能被编译成机器语言中类似DSP的指令，用于在处理器上执行。类似微控制器的指令与类似DSP的指令组合以产生程序，该程序分别具有虚拟语言部分和机器语言部分。当程序被执行时，程序的虚拟语言部分被转换为机器语言指令，并且直接执行程序的机器语言部分，使得特定应用程序的微处理器执行类DSP的指令和微控制器 - 喜欢指示

5. 发明授权

US5185694A Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies 失效
标题翻译：数据处理系统使用块数据输入的块移动指令数据块的宽度范围
公开(公告)号：US5185694A
公开(公告)日：1993-02-09
申请号：US371343
申请日：1989-06-26
申请人： Robin W. Edenfield , Ralph McGarity , Russell Reininger , William B. Ledbetter, Jr. , Van B. Shahan
发明人： Robin W. Edenfield , Ralph McGarity , Russell Reininger , William B. Ledbetter, Jr. , Van B. Shahan
IPC分类号： G06F12/08 , G06F9/315 , G06F13/28
CPC分类号： G06F9/30032
摘要： A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

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