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1. 发明申请

US20120198201A1 MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS 有权
标题翻译：具有可配置输入/输出端口的存储器模块
公开(公告)号：US20120198201A1
公开(公告)日：2012-08-02
申请号：US13445083
申请日：2012-04-12
申请人： Terry R. LEE , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. LEE , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F12/06
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.
摘要翻译：存储器模块耦合到多个控制器。存储器模块被配置为响应于来自控制器的特定控制器的第一命令，将多个数据输入/输出端口中的每一个配置为输入和输出中的至少一个。存储器模块被配置为响应于来自特定控制器的第二命令将自身分配到存储器分区中，使得每个存储器分区对应于相应的一个控制器。控制器的多个数据输入/输出端口中的每一个可配置为与存储器模块的输入/输出端口中的相应一个对应的输入和输出中的至少一个。第一和第二命令可以来自特定控制器，或者控制器可以并联到存储器模块。

2. 发明申请

US20090276545A1 MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS 有权
标题翻译：具有可配置输入/输出端口的存储器模块
公开(公告)号：US20090276545A1
公开(公告)日：2009-11-05
申请号：US12115047
申请日：2008-05-05
申请人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.
摘要翻译：存储器模块具有一个或多个存储器设备，与一个或多个存储器设备通信的控制器以及多个输入/输出端口。控制器配置为将每个输入/输出端口配置为输入，输出或双向输入/输出。

3. 发明授权

US08364856B2 Memory module with configurable input/output ports 有权
标题翻译：具有可配置输入/输出端口的内存模块
公开(公告)号：US08364856B2
公开(公告)日：2013-01-29
申请号：US13445083
申请日：2012-04-12
申请人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F13/14
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.
摘要翻译：存储器模块耦合到多个控制器。存储器模块被配置为响应于来自控制器的特定控制器的第一命令，将多个数据输入/输出端口中的每一个配置为输入和输出中的至少一个。存储器模块被配置为响应于来自特定控制器的第二命令将自身分配到存储器分区中，使得每个存储器分区对应于相应的一个控制器。控制器的多个数据输入/输出端口中的每一个可配置为与存储器模块的输入/输出端口中的相应一个对应的输入和输出中的至少一个。第一和第二命令可以来自特定控制器，或者控制器可以并联到存储器模块。

4. 发明授权

US08171181B2 Memory module with configurable input/output ports 有权
标题翻译：具有可配置输入/输出端口的内存模块
公开(公告)号：US08171181B2
公开(公告)日：2012-05-01
申请号：US12115047
申请日：2008-05-05
申请人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F13/14
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.
摘要翻译：存储器模块具有一个或多个存储器设备，与一个或多个存储器设备通信的控制器以及多个输入/输出端口。控制器配置为将每个输入/输出端口配置为输入，输出或双向输入/输出。

5. 发明授权

US06871253B2 Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection 有权
标题翻译：用于存储器子系统的数据传输电路具有选择性地连接或断开两个数据总线段以切换数据传输或I / O电路连接的切换电路
公开(公告)号：US06871253B2
公开(公告)日：2005-03-22
申请号：US09893616
申请日：2001-06-29
申请人： Roy Greeff , David Ovard , Terry R. Lee
发明人： Roy Greeff , David Ovard , Terry R. Lee
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F1/00
CPC分类号： G06F13/4265 , G06F13/1684 , G06F13/4086 , G06F13/4247 , Y02D10/14 , Y02D10/151
摘要： A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
摘要翻译：提供了一种方法和相关装置，用于改善使用开关的高速存储器总线的性能。通过使用分段式总线将系统组件连接在基本上不连续的配置中，其中总线段通过开关连接，基本上消除了由电线引起的总线反射。交换机在操作期间断开未使用的总线段，使得通信设备以基本上点对点的通信路径连接。

6. 发明授权

US06934785B2 High speed interface with looped bus 有权
标题翻译：高速接口带循环总线
公开(公告)号：US06934785B2
公开(公告)日：2005-08-23
申请号：US09741821
申请日：2000-12-22
申请人： Terry R. Lee , Roy Greeff , David Ovard
发明人： Terry R. Lee , Roy Greeff , David Ovard
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4265 , G06F13/1684 , G06F13/4086 , G06F13/4247 , Y02D10/14 , Y02D10/151
摘要： A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping bus through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.
摘要翻译：提供了一种方法和相关装置，用于通过基本上消除由电接头引起的总线反射来改善高速存储器总线的性能。通过使用循环总线将系统组件以基本上不连续的配置连接来连续通过每个设备的循环总线，基本上消除了短截线。本发明还提供一种能够实现不同技术的设备之间的数据通信的接口电路。接口电路连接到循环数据总线，并且包括用于为从循环数据总线接收的数据提供电压电平，编码类型和数据速率转换的电路，并用于在连接到接口电路的第二数据总线上使用。

7. 发明申请

US20080204108A1 DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES 有权
标题翻译：通过容量负载线耦合数字信号的去电子系统和方法
公开(公告)号：US20080204108A1
公开(公告)日：2008-08-28
申请号：US12113066
申请日：2008-04-30
申请人： Roy Greeff , David Ovard
发明人： Roy Greeff , David Ovard
IPC分类号： H03L5/00
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C11/4093
摘要： A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.
摘要翻译：用于去加强数字信号（诸如地址信号）的系统在将信号通过可能具有相对较大的电容的信号线传送之前提升一个时钟周期的信号电平。该系统可以包括延迟电路，该延迟电路在对应于时钟信号的一个周期的时段内延迟数字信号。该系统还可以包括第一乘法器电路，其通过将数字信号的第一和第二逻辑电平乘以第一乘法器来产生第一中间信号。类似地，第二乘法器电路通过将来自延迟电路的延迟信号的第一和第二逻辑电平乘以第二乘法器来产生第二中间信号。然后，组合电路从第一中间信号中减去第二中间信号，并且对结果信号进行电平调整以产生去加重的信号。

8. 发明申请

US20070290810A1 Backscatter interrogators, communication systems and backscatter communication methods 审中-公开
公开(公告)号：US20070290810A1
公开(公告)日：2007-12-20
申请号：US11847671
申请日：2007-08-30
申请人： David Ovard , Roy Greeff
发明人： David Ovard , Roy Greeff
IPC分类号： H04Q5/22
CPC分类号： G06K7/10366 , G06K7/0008 , G06K19/0723 , H01Q1/2208 , H04B1/707 , H04B7/22 , H04J13/0022
摘要： The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal.

9. 发明申请

US20070273425A1 De-emphasis system and method for coupling digital signals through capacitively loaded lines 有权
标题翻译：通过电容负载线耦合数字信号的去加重系统和方法
公开(公告)号：US20070273425A1
公开(公告)日：2007-11-29
申请号：US11442510
申请日：2006-05-25
申请人： Roy Greeff , David Ovard
发明人： Roy Greeff , David Ovard
IPC分类号： G06F7/44
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C11/4093
摘要： A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.
摘要翻译：用于去加强数字信号（诸如地址信号）的系统在将信号通过可能具有相对较大的电容的信号线传送之前提升一个时钟周期的信号电平。该系统可以包括延迟电路，该延迟电路在对应于时钟信号的一个周期的时段内延迟数字信号。该系统还可以包括第一乘法器电路，其通过将数字信号的第一和第二逻辑电平乘以第一乘法器来产生第一中间信号。类似地，第二乘法器电路通过将来自延迟电路的延迟信号的第一和第二逻辑电平乘以第二乘法器来产生第二中间信号。然后，组合电路从第一中间信号中减去第二中间信号，并且对结果信号进行电平调整以产生去加重的信号。

10. 发明申请

US20050235090A1 High speed interface with looped bus 审中-公开
公开(公告)号：US20050235090A1
公开(公告)日：2005-10-20
申请号：US11085270
申请日：2005-03-22
申请人： Terry Lee , Roy Greeff , David Ovard
发明人： Terry Lee , Roy Greeff , David Ovard
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4265 , G06F13/1684 , G06F13/4086 , G06F13/4247 , Y02D10/14 , Y02D10/151
摘要： A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping bus through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.

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