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1. 发明申请

US20050235090A1 High speed interface with looped bus 审中-公开
公开(公告)号：US20050235090A1
公开(公告)日：2005-10-20
申请号：US11085270
申请日：2005-03-22
申请人： Terry Lee , Roy Greeff , David Ovard
发明人： Terry Lee , Roy Greeff , David Ovard
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4265 , G06F13/1684 , G06F13/4086 , G06F13/4247 , Y02D10/14 , Y02D10/151
摘要： A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping bus through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.

2. 发明申请

US20120198201A1 MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS 有权
标题翻译：具有可配置输入/输出端口的存储器模块
公开(公告)号：US20120198201A1
公开(公告)日：2012-08-02
申请号：US13445083
申请日：2012-04-12
申请人： Terry R. LEE , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. LEE , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F12/06
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.
摘要翻译：存储器模块耦合到多个控制器。存储器模块被配置为响应于来自控制器的特定控制器的第一命令，将多个数据输入/输出端口中的每一个配置为输入和输出中的至少一个。存储器模块被配置为响应于来自特定控制器的第二命令将自身分配到存储器分区中，使得每个存储器分区对应于相应的一个控制器。控制器的多个数据输入/输出端口中的每一个可配置为与存储器模块的输入/输出端口中的相应一个对应的输入和输出中的至少一个。第一和第二命令可以来自特定控制器，或者控制器可以并联到存储器模块。

3. 发明申请

US20090276545A1 MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS 有权
标题翻译：具有可配置输入/输出端口的存储器模块
公开(公告)号：US20090276545A1
公开(公告)日：2009-11-05
申请号：US12115047
申请日：2008-05-05
申请人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.
摘要翻译：存储器模块具有一个或多个存储器设备，与一个或多个存储器设备通信的控制器以及多个输入/输出端口。控制器配置为将每个输入/输出端口配置为输入，输出或双向输入/输出。

4. 发明申请

US20080204108A1 DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES 有权
标题翻译：通过容量负载线耦合数字信号的去电子系统和方法
公开(公告)号：US20080204108A1
公开(公告)日：2008-08-28
申请号：US12113066
申请日：2008-04-30
申请人： Roy Greeff , David Ovard
发明人： Roy Greeff , David Ovard
IPC分类号： H03L5/00
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C11/4093
摘要： A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.
摘要翻译：用于去加强数字信号（诸如地址信号）的系统在将信号通过可能具有相对较大的电容的信号线传送之前提升一个时钟周期的信号电平。该系统可以包括延迟电路，该延迟电路在对应于时钟信号的一个周期的时段内延迟数字信号。该系统还可以包括第一乘法器电路，其通过将数字信号的第一和第二逻辑电平乘以第一乘法器来产生第一中间信号。类似地，第二乘法器电路通过将来自延迟电路的延迟信号的第一和第二逻辑电平乘以第二乘法器来产生第二中间信号。然后，组合电路从第一中间信号中减去第二中间信号，并且对结果信号进行电平调整以产生去加重的信号。

5. 发明申请

US20070290810A1 Backscatter interrogators, communication systems and backscatter communication methods 审中-公开
公开(公告)号：US20070290810A1
公开(公告)日：2007-12-20
申请号：US11847671
申请日：2007-08-30
申请人： David Ovard , Roy Greeff
发明人： David Ovard , Roy Greeff
IPC分类号： H04Q5/22
CPC分类号： G06K7/10366 , G06K7/0008 , G06K19/0723 , H01Q1/2208 , H04B1/707 , H04B7/22 , H04J13/0022
摘要： The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal.

6. 发明申请

US20070273425A1 De-emphasis system and method for coupling digital signals through capacitively loaded lines 有权
标题翻译：通过电容负载线耦合数字信号的去加重系统和方法
公开(公告)号：US20070273425A1
公开(公告)日：2007-11-29
申请号：US11442510
申请日：2006-05-25
申请人： Roy Greeff , David Ovard
发明人： Roy Greeff , David Ovard
IPC分类号： G06F7/44
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C11/4093
摘要： A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.
摘要翻译：用于去加强数字信号（诸如地址信号）的系统在将信号通过可能具有相对较大的电容的信号线传送之前提升一个时钟周期的信号电平。该系统可以包括延迟电路，该延迟电路在对应于时钟信号的一个周期的时段内延迟数字信号。该系统还可以包括第一乘法器电路，其通过将数字信号的第一和第二逻辑电平乘以第一乘法器来产生第一中间信号。类似地，第二乘法器电路通过将来自延迟电路的延迟信号的第一和第二逻辑电平乘以第二乘法器来产生第二中间信号。然后，组合电路从第一中间信号中减去第二中间信号，并且对结果信号进行电平调整以产生去加重的信号。

7. 发明申请

US20070290808A1 Backscatter interrogators, communication systems and backscatter communication methods 审中-公开
公开(公告)号：US20070290808A1
公开(公告)日：2007-12-20
申请号：US11847654
申请日：2007-08-30
申请人： David Ovard , Roy Greeff
发明人： David Ovard , Roy Greeff
IPC分类号： H04Q5/22 , H04B1/69
CPC分类号： G06K7/10366 , G06K7/0008 , G06K19/0723 , H01Q1/2208 , H04B1/707 , H04B7/22 , H04J13/0022
摘要： The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal.

8. 发明申请

US20070290806A1 Phase Shifters, Interrogators, Methods Of Shifting A Phase Angle Of A Signal, And Methods Of Operating An Interrogator 失效
标题翻译：移相器，询问器，移位信号的相位角的方法以及操作询问器的方法
公开(公告)号：US20070290806A1
公开(公告)日：2007-12-20
申请号：US11845902
申请日：2007-08-28
申请人： Roy Greeff , David Ovard
发明人： Roy Greeff , David Ovard
IPC分类号： H04Q5/22 , H04Q1/00
CPC分类号： H04B1/525 , G01S13/751 , G06K7/0008 , G07C9/00309 , G07C2009/00373 , G07C2009/00793 , H04B5/0056
摘要： The present invention includes phase shifters, interrogators, methods of shifting a phase angle of a signal, and methods of operating an interrogator. One aspect of the present invention provides a phase shifter including a first power divider configured to receive a signal and provide plural quadrature components of the signal; plural mixers coupled with the first power divider and configured to scale the quadrature components using a phase shift angle; and a second power divider coupled with the mixers and configured to combine the scaled quadrature components to shift the phase angle of the input signal by the phase shift angle.
摘要翻译：本发明包括移相器，询问器，移位信号的相位角的方法以及操作询问器的方法。本发明的一个方面提供了一种移相器，包括：第一功率分配器，被配置为接收信号并提供信号的多个正交分量; 多个混频器，与第一功率分配器耦合并被配置为使用相移角缩放正交分量; 以及与所述混频器耦合并被配置为组合所述经比例缩放的正交分量以将所述输入信号的相位角移位所述相移角的第二功率分配器。

9. 发明申请

US20060045206A1 Method and system for generating reference voltages for signal receivers 有权
公开(公告)号：US20060045206A1
公开(公告)日：2006-03-02
申请号：US10930543
申请日：2004-08-30
申请人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
IPC分类号： H04L27/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

10. 发明授权

US08364856B2 Memory module with configurable input/output ports 有权
标题翻译：具有可配置输入/输出端口的内存模块
公开(公告)号：US08364856B2
公开(公告)日：2013-01-29
申请号：US13445083
申请日：2012-04-12
申请人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
发明人： Terry R. Lee , David Ovard , Roy Greeff , Robert N. Leibowitz , Victor Tsai
IPC分类号： G06F13/14
CPC分类号： G11C7/1045 , G11C5/00
摘要： A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.
摘要翻译：存储器模块耦合到多个控制器。存储器模块被配置为响应于来自控制器的特定控制器的第一命令，将多个数据输入/输出端口中的每一个配置为输入和输出中的至少一个。存储器模块被配置为响应于来自特定控制器的第二命令将自身分配到存储器分区中，使得每个存储器分区对应于相应的一个控制器。控制器的多个数据输入/输出端口中的每一个可配置为与存储器模块的输入/输出端口中的相应一个对应的输入和输出中的至少一个。第一和第二命令可以来自特定控制器，或者控制器可以并联到存储器模块。

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