专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070135647A1 Methods for synthesis of 3-amino-1-arylpropyl indoles 失效
标题翻译：合成3-氨基-1-芳基丙基吲哚的方法
公开(公告)号：US20070135647A1
公开(公告)日：2007-06-14
申请号：US11605648
申请日：2006-11-29
申请人： Terrence Connolly , Robert Farrell , Eric Humphreys , Stephen Lynch , Keshab Sarma
发明人： Terrence Connolly , Robert Farrell , Eric Humphreys , Stephen Lynch , Keshab Sarma
IPC分类号： C07D209/18
CPC分类号： C07D209/14 , C07D209/18
摘要： A method comprising: hydrogenating an indole propionamide compound of formula h with vitride, to form an aminopropyl indole compound of formula i wherein m, Ar, R1 and R2 are as defined herein. The compounds prepared by the method of the invention are useful as monoamine reuptake inhibitors useful for treatment of CNS indications.
摘要翻译：一种方法，包括：用维生素氢化式h的吲哚丙酰胺化合物，形成其中m，Ar，R 1和R 2的氨基丙基吲哚化合物为本文定义。通过本发明方法制备的化合物可用作用于治疗CNS适应症的单胺再摄取抑制剂。

2. 发明申请

US20110097597A1 IMMERSION TIN SILVER PLATING IN ELECTRONICS MANUFACTURE 有权
标题翻译：电子制造中的镀银镀银
公开(公告)号：US20110097597A1
公开(公告)日：2011-04-28
申请号：US12607375
申请日：2009-10-28
申请人： Yung-Herng Yau , Xingping Wang , Cai Wang , Robert Farrell , Pingping Ye , Edward J. Kudrak, JR. , Karl F. Wengenroth , Joseph A. Abys
发明人： Yung-Herng Yau , Xingping Wang , Cai Wang , Robert Farrell , Pingping Ye , Edward J. Kudrak, JR. , Karl F. Wengenroth , Joseph A. Abys
IPC分类号： B32B15/01 , B05D1/18
CPC分类号： C23C18/54 , C23C18/48 , Y10T428/12715
摘要： A method is provided for depositing a whisker resistant tin-based coating layer on a surface of a copper substrate. The method is useful for preparing an article comprising a copper substrate having a surface; and a tin-based coating layer on the surface of the substrate, wherein the tin-based coating layer has a thickness between 0.5 micrometers and 1.5 micrometers and has a resistance to formation of copper-tin intermetallics, wherein said resistance to formation of copper-tin intermetallics is characterized in that, upon exposure of the article to at least seven heating and cooling cycles in which each cycle comprises subjecting the article to a temperature of at least 217° C. followed by cooling to a temperature between about 20° C. and about 28° C., there remains a region of the tin coating layer that is free of copper that is at least 0.25 micrometers thick.
摘要翻译：提供了在铜基板的表面上沉积耐晶须锡基涂层的方法。该方法可用于制备包含具有表面的铜基材的制品; 以及在所述基板的表面上的锡基涂层，其中所述锡基涂层的厚度为0.5微米至1.5微米，并且具有形成铜 - 锡金属间化合物的阻力，其中所述耐铜 - 锡金属间化合物的特征在于，当制品暴露于至少七个加热和冷却循环时，其中每个循环包括使制品经受至少217℃的温度，然后冷却至约20℃的温度。并且约28℃，仍然存在不超过至少0.25微米厚的铜的锡涂层的区域。

3. 发明申请

US20070093073A1 Technique for the growth and fabrication of semipolar (Ga,A1,In,B)N thin films, heterostructures, and devices 有权
标题翻译：用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的技术
公开(公告)号：US20070093073A1
公开(公告)日：2007-04-26
申请号：US11444946
申请日：2006-06-01
申请人： Robert Farrell , Troy Baker , Arpan Chakraborty , Benjamin Haskell , P. Pattison , Rajat Sharma , Umesh Mishra , Steven DenBaars , James Speck , Shuji Nakamura
发明人： Robert Farrell , Troy Baker , Arpan Chakraborty , Benjamin Haskell , P. Pattison , Rajat Sharma , Umesh Mishra , Steven DenBaars , James Speck , Shuji Nakamura
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L33/16 , B82Y20/00 , C30B23/025 , C30B25/18 , C30B29/403 , H01L21/02389 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L33/0004 , H01L33/0062 , H01L33/007 , H01L33/02 , H01S5/0422 , H01S5/2201 , H01S5/3202 , H01S5/34333 , H01S2304/04
摘要： A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.
摘要翻译：一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

4. 发明授权

US5510740A Method for synchronizing clocks upon reset 失效
标题翻译：复位时同步时钟的方法
公开(公告)号：US5510740A
公开(公告)日：1996-04-23
申请号：US272879
申请日：1994-07-11
申请人： Robert Farrell , Sharad Mehrotra
发明人： Robert Farrell , Sharad Mehrotra
IPC分类号： H03K5/135 , H03K5/13
CPC分类号： H03K5/135
摘要： A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.
摘要翻译：同步时钟电路接收时钟信号，并且根据所接收的时钟信号，在复位时提供相对于所接收的时钟信号具有已知相位关系的分频时钟信号。为了提供已知的相位关系，并且因此使接收到的时钟信号和分频时钟信号同步，可选地跳过分频下降时钟信号的周期。复位信号被调节并应用于主动边沿检测器。根据主动边沿检测器可选择地跳过分频下降时钟的周期。

5. 发明申请

US20080041342A1 Fuel rail 失效
标题翻译：燃油轨
公开(公告)号：US20080041342A1
公开(公告)日：2008-02-21
申请号：US11890417
申请日：2007-08-06
申请人： George Kochanowski , Stephen Purvines , Robert Farrell
发明人： George Kochanowski , Stephen Purvines , Robert Farrell
IPC分类号： F02M41/00
CPC分类号： F02M55/025 , F02M61/16
摘要： Embodiments include a fuel rail and method for making the fuel rail. Embodiments of the fuel rail include an elongate lining having a surface defining a lumen, a pressure port having a lumen in fluid communication with the lumen of the elongate lining, and a thermoset composite body surrounding at least a portion of the elongate lining and the pressure port.
摘要翻译：实施例包括燃料轨和用于制造燃料轨的方法。燃料轨道的实施例包括具有限定内腔的表面的细长衬里，具有与细长衬里的内腔流体连通的内腔的压力端口以及围绕细长衬里和压力的至少一部分的热固性复合体港口。

6. 发明申请

US20050144423A1 Methods and apparatus for address generation in processors 有权
标题翻译：处理器中地址生成的方法和设备
公开(公告)号：US20050144423A1
公开(公告)日：2005-06-30
申请号：US10747764
申请日：2003-12-29
申请人： Rajesh Patel , Robert Farrell , James Phillips , Belliappa Kuttanna , Scott Siers , T.W. Griffith
发明人： Rajesh Patel , Robert Farrell , James Phillips , Belliappa Kuttanna , Scott Siers , T.W. Griffith
IPC分类号： G06F9/355 , G06F9/38 , G06F12/06
CPC分类号： G06F9/342 , G06F9/355 , G06F9/3842 , G06F9/3861
摘要： Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.
摘要翻译：公开了在处理器中产生地址的方法和装置。本文公开的示例性地址生成器包括：加法器，用于添加第一地址分量和第二地址分量以产生地址;校正指示符，用于指示地址是否正确;以及控制输入，用于修改加法器的操作。

7. 发明申请

US20050038533A1 System and method for simplifying and manipulating k-partite graphs 失效
标题翻译：用于简化和操纵k-partite图的系统和方法
公开(公告)号：US20050038533A1
公开(公告)日：2005-02-17
申请号：US10496778
申请日：2002-04-05
申请人： Robert Farrell , Douglas Gordin
发明人： Robert Farrell , Douglas Gordin
IPC分类号： G06F17/30 , G06F17/00
CPC分类号： G06F17/30958 , G06Q50/01
摘要： The system has a collection of a plurality of objects. Each object defines a node in a k-partite graph, such that, the nodes can e divided into a number of mutually exclusive sets such that all of the nodes are in exactly one of the sets; further edges occur only between nodes in different sets; The system also has a simplification process that aggregates one or more of the nodes into one or more categories and identifies a category node corresponding to each category. The category node inherits the mode and the edges of all the nodes in the respective category. Further, the system contains Directed Acyclic Graphs Indices (DAGIs) whose nodes may have a 1-1 mapping with the nodes in the k-partite graph. These indices can be used to aggregate and hide nodes in the k-partite graph. Aggregation occurs by selecting one or more non-leaf nodes in the DAGI and aggregating all descendent nodes. Hiding occurs by selecting some set of DAGI nodes, thus selecting some corresponding set of nodes in the k-partite graph, and requesting this set of nodes be hidden which effectively removes them from further consideration until they are restored by explicit request.
摘要翻译：该系统具有多个对象的集合。每个对象定义了k分图中的节点，使得节点可以被分成多个互斥集合，使得所有节点都在正好一组中; 另外的边缘仅发生在不同集合中的节点之间; 该系统还具有将一个或多个节点聚合成一个或多个类别并识别与每个类别对应的类别节点的简化过程。类别节点继承相应类别中所有节点的模式和边。此外，该系统包含定向非循环图指数（DAGI），其节点可以与k-部分图中的节点具有1-1映射。这些索引可用于聚合和隐藏k-partite图中的节点。通过在DAGI中选择一个或多个非叶节点并聚合所有后代节点来进行聚合。通过选择一些DAGI节点进行隐藏，从而在k-partite图中选择一些对应的节点组，并且请求这组节点被隐藏，这有效地将它们从进一步的考虑中去除，直到它们被显式请求恢复。

8. 发明授权

US5664153A Page open/close scheme based on high order address bit and likelihood of page access 失效
标题翻译：基于高位地址位的页面打开/关闭方案和页面访问的可能性
公开(公告)号：US5664153A
公开(公告)日：1997-09-02
申请号：US521007
申请日：1995-08-30
申请人： Robert Farrell
发明人： Robert Farrell
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0215
摘要： When writing a computer program which accesses a page of memory a programmer may know whether the next memory access is likely to be in the same page of memory. According to a preferred embodiment, program instructions indicate whether the next access is likely to be in the same page of memory. When these instructions are assembled, the assembler puts page control information in an unused high order address bit of the memory access. When the program is executed a memory controller in the system executing the program reads this page control bit and determines whether to close the page after access or leave it open for the next access bit.
摘要翻译：当编写访问存储器页面的计算机程序时，程序员可以知道下一个存储器访问是否可能在同一页存储器中。根据优选实施例，程序指令指示下一次访问是否可能在同一页的存储器中。当组装这些指令时，汇编器将页面控制信息放置在存储器访问的未使用的高位地址位中。当执行程序时，执行程序的系统中的存储器控制器读取该页面控制位，并确定是否在访问之后关闭页面或者将其打开以用于下一访问位。

9. 发明授权

US5519345A Reconfigurable interrupt device and method 失效
标题翻译：可重构中断设备和方法
公开(公告)号：US5519345A
公开(公告)日：1996-05-21
申请号：US378920
申请日：1995-01-26
申请人： Robert Farrell , Himanshu Sanghavi , Ashish Pandya
发明人： Robert Farrell , Himanshu Sanghavi , Ashish Pandya
IPC分类号： H03K5/135 , H03K19/0175 , H03K19/20
CPC分类号： H03K5/135
摘要： Reconfigurable interrupt circuitry may provide differing interrupt output signals to various interrupt receiving devices which are adapted to be driven by interrupt circuits having differing drive characteristics. Control signals representative of the device characteristics of the interrupt receiving device are applied to the reconfigurable interrupt circuitry and output characteristics of the reconfigurable interrupt circuitry are selected according to the control signals. In this manner the reconfigurable interrupt circuitry may by adapted to drive interrupt receiving devices which are compatible with active high interrupt output, active low interrupt output, open drain interrupt output, totem pole interrupt output, tristate interrupt output and non tristate interrupt output. The selected configuration of the reconfigurable interrupt circuitry is determined by writing to registers which may be placed within the memory space of external devices so that the external devices may configure the interrupt according to their own characteristics.
摘要翻译：可重配置中断电路可以向适合于由具有不同驱动特性的中断电路驱动的各种中断接收装置提供不同的中断输出信号。代表中断接收装置的装置特性的控制信号被应用于可重构中断电路，并根据控制信号选择可重构中断电路的输出特性。以这种方式，可重构中断电路可以适用于驱动与高电平有效中断输出，低电平有效中断输出，开漏中断输出，图腾柱中断输出，三态中断输出和非三态中断输出兼容的中断接收器件。通过写入可以放置在外部设备的存储器空间内的寄存器来确定可重配置中断电路的所选配置，使得外部设备可以根据其自己的特性来配置中断。

10. 发明申请

US20150178982A1 FOUR CORNER HIGH PERFORMANCE DEPTH TEST 有权
标题翻译：四角高性能深度测试
公开(公告)号：US20150178982A1
公开(公告)日：2015-06-25
申请号：US14136290
申请日：2013-12-20
申请人： Robert Farrell , Vasanth Ranganathan , Karol Carlo A Szerszen
发明人： Robert Farrell , Vasanth Ranganathan , Karol Carlo A Szerszen
IPC分类号： G06T15/40
CPC分类号： G06T15/405 , G06T2210/12
摘要： One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous.
摘要翻译：描述了一种或多种用于图形处理器中的多像素/样本级深度测试的装置和方法。在实施例中，基于在光栅化器瓦片内的点亮像素或样本的图案来确定将要执行深度测试的可变大小的边界框。可以在源深度数据边界内的源深度数据平面和目的地深度平面之间执行多角度深度测试，其中目的地深度数据在源数据界限内是连续的。可以响应于不连续的目的地数据来执行基于范围的深度测试。在深度测试中存在的源深度数据可以以压缩平面方程式格式存储，以响应于源数据界限内的源数据是连续的，并且如果不连续，则可以将其存储为最小/最大深度数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式