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1. 发明申请

US20150178982A1 FOUR CORNER HIGH PERFORMANCE DEPTH TEST 有权
标题翻译：四角高性能深度测试
公开(公告)号：US20150178982A1
公开(公告)日：2015-06-25
申请号：US14136290
申请日：2013-12-20
申请人： Robert Farrell , Vasanth Ranganathan , Karol Carlo A Szerszen
发明人： Robert Farrell , Vasanth Ranganathan , Karol Carlo A Szerszen
IPC分类号： G06T15/40
CPC分类号： G06T15/405 , G06T2210/12
摘要： One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous.
摘要翻译：描述了一种或多种用于图形处理器中的多像素/样本级深度测试的装置和方法。在实施例中，基于在光栅化器瓦片内的点亮像素或样本的图案来确定将要执行深度测试的可变大小的边界框。可以在源深度数据边界内的源深度数据平面和目的地深度平面之间执行多角度深度测试，其中目的地深度数据在源数据界限内是连续的。可以响应于不连续的目的地数据来执行基于范围的深度测试。在深度测试中存在的源深度数据可以以压缩平面方程式格式存储，以响应于源数据界限内的源数据是连续的，并且如果不连续，则可以将其存储为最小/最大深度数据。

2. 发明申请

US20200258292A1 APPARATUS AND METHOD FOR OPTIMIZING A HIERARCHICAL DEPTH BUFFER 审中-公开
公开(公告)号：US20200258292A1
公开(公告)日：2020-08-13
申请号：US16275270
申请日：2019-02-13
申请人： Vasanth Ranganathan , Saikat Mandal
发明人： Vasanth Ranganathan , Saikat Mandal
IPC分类号： G06T15/40
摘要： Apparatus and method for optimizing a hierarchical depth buffer. For example, one embodiment of a method comprises: rasterizing primitives of a current graphics image to generate pixels; generating coverage data associated with a first primitive to identify pixels in a first tile of pixels which are partially covered or fully covered by the first primitive; estimating potential minimum (min) and maximum (max) values for the first primitive at edges of a bounding box surrounding the first primitive within the first tile; and adjusting the potential min and/or max values to be closer to actual min and/or max values, respectively, upon a determination that the potential min and/or max values identify one or more pixels which are not partially or fully covered by the primitive.

3. 发明申请

US20180286113A1 HIERARCHICAL DEPTH BUFFER BACK ANNOTATON 审中-公开
公开(公告)号：US20180286113A1
公开(公告)日：2018-10-04
申请号：US15477049
申请日：2017-04-01
申请人： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker
发明人： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker
IPC分类号： G06T15/40 , G06T7/529 , G06T15/20 , G06T11/00 , G06T11/40
CPC分类号： G06T15/405 , G06T15/005
摘要： Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.

4. 发明授权

US06931484B2 Method and apparatus for handling memory refresh and maintenance operations 有权
标题翻译：用于处理存储器刷新和维护操作的方法和装置
公开(公告)号：US06931484B2
公开(公告)日：2005-08-16
申请号：US10134230
申请日：2002-04-25
申请人： Vasanth Ranganathan , Alankar Saxena
发明人： Vasanth Ranganathan , Alankar Saxena
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1636
摘要： Embodiments of the present invention provide a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications. In particular, refresh and memory operations are executed in two stages. A first stage includes, but is not limited to, memory channel temperature calibration, RAC auto current calibration, and RAC auto temperature calibration. First stage operations are scheduled when the primary display is not requesting data from memory, such as when the display is in its vertical blanking interval. A second stage includes, but is not limited to, memory refreshes and memory current calibration. These operations are scheduled when there are no display streams (primary and secondary) or when display is requesting in a low priority mode.
摘要翻译：本发明的实施例提供了一种用于处理图形和其他应用的存储器刷新和维护操作的方法和装置。特别地，刷新和存储器操作分两个阶段执行。第一阶段包括但不限于内存通道温度校准，RAC自动电流校准和RAC自动温度校准。当主显示器不从存储器请求数据时，例如当显示器处于其垂直消隐间隔时，调度第一阶段操作。第二阶段包括但不限于存储刷新和存储器电流校准。当没有显示流（主要和次要）或显示在低优先级模式下请求时，这些操作将被调度。

5. 发明申请

US20180285120A1 REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE 审中-公开
公开(公告)号：US20180285120A1
公开(公告)日：2018-10-04
申请号：US15477030
申请日：2017-04-01
申请人： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
发明人： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC分类号： G06F9/38 , G06F9/345 , G06F9/30 , G06F12/084 , G06T1/60 , G06T1/20 , G09G5/36
CPC分类号： G09G5/363 , G06F9/461 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F2212/1024 , G06F2212/1028 , G06F2212/455 , G09G5/001 , G09G2340/02 , G09G2350/00 , G09G2352/00 , G09G2360/08 , G09G2360/121
摘要： A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

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