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1. 发明授权

US06609232B2 Logic compound method and logic compound apparatus 失效
标题翻译：逻辑复合法和逻辑复合器
公开(公告)号：US06609232B2
公开(公告)日：2003-08-19
申请号：US09791818
申请日：2001-02-26
申请人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
发明人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.
摘要翻译：在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

2. 发明授权

US06915413B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06915413B2
公开(公告)日：2005-07-05
申请号：US10101480
申请日：2002-03-20
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F7/36 , G06F9/45 , G06F17/30
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

3. 发明授权

US06986029B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06986029B2
公开(公告)日：2006-01-10
申请号：US10201249
申请日：2002-07-24
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F7/06 , G06F15/76
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

4. 发明申请

US20050198471A1 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 审中-公开
标题翻译：用于读出压缩指令代码的微控制器和用于压缩指令代码并存储在其中的程序存储器
公开(公告)号：US20050198471A1
公开(公告)日：2005-09-08
申请号：US11117509
申请日：2005-04-29
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
摘要翻译：微控制器包括用于存储出现在程序中的指令代码的字典存储器和用于存储从程序中包括的每个指令代码转换的压缩代码的压缩代码存储器。每个压缩代码的字长足够长以识别程序中包含的所有指令代码。每个压缩代码具有指示存储相关联的指令代码的字典存储器中的地址的值。微控制器响应于指定代码读取请求，其指定压缩代码的地址以读取存储在压缩代码存储器中的指定地址中的压缩代码，并且随后读取存储在由压缩代码存储器指示的地址中的指令代码字典内存中的压缩代码。

5. 发明申请

US20090024777A1 ARBITER AND ARBITRATION METHOD OF MULTIPLE DATA ACCESSES 失效
标题翻译：多数据访问的ARBITER和仲裁方法
公开(公告)号：US20090024777A1
公开(公告)日：2009-01-22
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F13/366
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以抑制高优先级访问处理的平均延迟增加来降低低优先级访问的平均处理时间，共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

6. 发明申请

US20080077745A1 Data processing device 审中-公开
标题翻译：数据处理装置
公开(公告)号：US20080077745A1
公开(公告)日：2008-03-27
申请号：US11890902
申请日：2007-08-07
申请人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
发明人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
IPC分类号： G06F12/02
CPC分类号： G06F12/0802 , G06F12/08 , G06F2212/401
摘要： A data processing device that does not depend on the type of data, has wide application range, and can reduce memory access in data transfer via a buffer arranged in a memory is provided. In a data processing device including a plurality of data processing units and a memory commonly accessed by the data processing units, the data processing units transfer the transfer data via the memory, the transfer data and the compressed data of the transfer data are held in the memory. When read request for the data is issued, the compressed data is expanded and the expanded data is stored in the expanding data buffer. While the compressed data is being expanded, the original data is read from the memory, and after the expanded data is stored in the expanding data buffer, the expanded data is read from the expanding data buffer.
摘要翻译：提供了不依赖于数据类型的数据处理设备，具有广泛的应用范围，并且可以经由布置在存储器中的缓冲器的数据传输中减少存储器访问。在包括多个数据处理单元和由数据处理单元共同访问的存储器的数据处理设备中，数据处理单元经由存储器传送传送数据，传送数据和传送数据的压缩数据保存在记忆。当发出对数据的读取请求时，压缩数据被扩展，扩展数据被存储在扩展数据缓冲器中。当压缩数据被扩展时，从存储器读取原始数据，并且在扩展数据被存储在扩展数据缓冲器中之后，从扩展数据缓冲器中读出扩展数据。

7. 发明授权

US07904626B2 Arbiter and arbitration method of multiple data accesses 失效
标题翻译：多重数据访问的仲裁和仲裁方法
公开(公告)号：US07904626B2
公开(公告)日：2011-03-08
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F12/00
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以通过抑制高优先级访问处理的平均延迟增加来减少低优先级访问的平均处理时间共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

8. 发明申请

US20050027921A1 Information processing apparatus capable of prefetching instructions 审中-公开
标题翻译：能够预取指令的信息处理装置
公开(公告)号：US20050027921A1
公开(公告)日：2005-02-03
申请号：US10842638
申请日：2004-05-11
申请人： Teppei Hirotsu , Kotaro Shimamura , Noboru Sugihara , Yasuhiro Nakatsuka , Teruaki Sakata
发明人： Teppei Hirotsu , Kotaro Shimamura , Noboru Sugihara , Yasuhiro Nakatsuka , Teruaki Sakata
IPC分类号： G06F9/38 , G11C5/00
CPC分类号： G06F9/3814 , G06F9/3802
摘要： A prefetch address calculation unit detects a branch instruction and a data access instruction to be reliably executed from a series of instruction included in an entry that is stored in a buffer at 1 cycle and outputs a prefetch request of its target address to a control unit. Then, decoding types of the series of instruction that is included in the entry, and setting it at an instruction type flag, the prefetch address calculation unit masks the output of the instruction type flag that has been executed by using an address signal of the instruction that is being executing presently and outputs a location of the instruction for issuing a prefetch request. By a signal from a control unit, the prefetch address calculation unit clears an instruction type flag corresponding to the instruction that issued the prefetch request.
摘要翻译：预取地址计算单元从包含在存储在缓冲器中的条目中的一系列指令以1个周期检测可靠地执行的分支指令和数据访问指令，并将其目标地址的预取请求输出到控制单元。然后，对包含在条目中的一系列指令进行解码，并将其设置为指令类型标志，预取地址计算单元通过使用指令的地址信号来掩蔽已经执行的指令类型标志的输出正在执行中，并且输出用于发出预取请求的指令的位置。通过来自控制单元的信号，预取地址计算单元清除与发出预取请求的指令相对应的指令类型标志。

9. 发明授权

US06792583B1 Information processing apparatus, information processing system, and storage media 失效
标题翻译：信息处理装置，信息处理系统和存储介质
公开(公告)号：US06792583B1
公开(公告)日：2004-09-14
申请号：US09501977
申请日：2000-02-11
申请人： Yoshitaka Takahashi , Kotaro Shimamura , Takashi Hotta , Teppei Hirotsu , Katsuichi Tomobe
发明人： Yoshitaka Takahashi , Kotaro Shimamura , Takashi Hotta , Teppei Hirotsu , Katsuichi Tomobe
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.
摘要翻译：在信息处理装置中，不知道LSI的设计者的用户在不降低LSI的性能的情况下修改LSI的布局图。设计LSI的设计者使用电路设计装置来存储包括构成LSI的每个块的功能的电路信息，关于块的分配的平面布置图以及作为设计者的专有技术的评估指标，与彼此。用户使用平面图修改装置来修改平面布置图并根据评价指标来评估修改的平面图。

10. 发明申请

US20100131741A1 MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT 有权
标题翻译：具有检测加工结果的多核微型计算机
公开(公告)号：US20100131741A1
公开(公告)日：2010-05-27
申请号：US12610422
申请日：2009-11-02
申请人： Hiromichi YAMADA , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
发明人： Hiromichi YAMADA , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
IPC分类号： G06F9/30 , G06F9/44 , G06F9/38
CPC分类号： G06F11/1608 , G06F11/004 , G06F11/1641 , G06F11/1687 , G06F2201/83 , G06F2201/845
摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.
摘要翻译：一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

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