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1. 发明申请

US20050027921A1 Information processing apparatus capable of prefetching instructions 审中-公开
标题翻译：能够预取指令的信息处理装置
公开(公告)号：US20050027921A1
公开(公告)日：2005-02-03
申请号：US10842638
申请日：2004-05-11
申请人： Teppei Hirotsu , Kotaro Shimamura , Noboru Sugihara , Yasuhiro Nakatsuka , Teruaki Sakata
发明人： Teppei Hirotsu , Kotaro Shimamura , Noboru Sugihara , Yasuhiro Nakatsuka , Teruaki Sakata
IPC分类号： G06F9/38 , G11C5/00
CPC分类号： G06F9/3814 , G06F9/3802
摘要： A prefetch address calculation unit detects a branch instruction and a data access instruction to be reliably executed from a series of instruction included in an entry that is stored in a buffer at 1 cycle and outputs a prefetch request of its target address to a control unit. Then, decoding types of the series of instruction that is included in the entry, and setting it at an instruction type flag, the prefetch address calculation unit masks the output of the instruction type flag that has been executed by using an address signal of the instruction that is being executing presently and outputs a location of the instruction for issuing a prefetch request. By a signal from a control unit, the prefetch address calculation unit clears an instruction type flag corresponding to the instruction that issued the prefetch request.
摘要翻译：预取地址计算单元从包含在存储在缓冲器中的条目中的一系列指令以1个周期检测可靠地执行的分支指令和数据访问指令，并将其目标地址的预取请求输出到控制单元。然后，对包含在条目中的一系列指令进行解码，并将其设置为指令类型标志，预取地址计算单元通过使用指令的地址信号来掩蔽已经执行的指令类型标志的输出正在执行中，并且输出用于发出预取请求的指令的位置。通过来自控制单元的信号，预取地址计算单元清除与发出预取请求的指令相对应的指令类型标志。

2. 发明授权

US07904626B2 Arbiter and arbitration method of multiple data accesses 失效
标题翻译：多重数据访问的仲裁和仲裁方法
公开(公告)号：US07904626B2
公开(公告)日：2011-03-08
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F12/00
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以通过抑制高优先级访问处理的平均延迟增加来减少低优先级访问的平均处理时间共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

3. 发明申请

US20090024777A1 ARBITER AND ARBITRATION METHOD OF MULTIPLE DATA ACCESSES 失效
标题翻译：多数据访问的ARBITER和仲裁方法
公开(公告)号：US20090024777A1
公开(公告)日：2009-01-22
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F13/366
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以抑制高优先级访问处理的平均延迟增加来降低低优先级访问的平均处理时间，共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

4. 发明申请

US20080077745A1 Data processing device 审中-公开
标题翻译：数据处理装置
公开(公告)号：US20080077745A1
公开(公告)日：2008-03-27
申请号：US11890902
申请日：2007-08-07
申请人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
发明人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
IPC分类号： G06F12/02
CPC分类号： G06F12/0802 , G06F12/08 , G06F2212/401
摘要： A data processing device that does not depend on the type of data, has wide application range, and can reduce memory access in data transfer via a buffer arranged in a memory is provided. In a data processing device including a plurality of data processing units and a memory commonly accessed by the data processing units, the data processing units transfer the transfer data via the memory, the transfer data and the compressed data of the transfer data are held in the memory. When read request for the data is issued, the compressed data is expanded and the expanded data is stored in the expanding data buffer. While the compressed data is being expanded, the original data is read from the memory, and after the expanded data is stored in the expanding data buffer, the expanded data is read from the expanding data buffer.
摘要翻译：提供了不依赖于数据类型的数据处理设备，具有广泛的应用范围，并且可以经由布置在存储器中的缓冲器的数据传输中减少存储器访问。在包括多个数据处理单元和由数据处理单元共同访问的存储器的数据处理设备中，数据处理单元经由存储器传送传送数据，传送数据和传送数据的压缩数据保存在记忆。当发出对数据的读取请求时，压缩数据被扩展，扩展数据被存储在扩展数据缓冲器中。当压缩数据被扩展时，从存储器读取原始数据，并且在扩展数据被存储在扩展数据缓冲器中之后，从扩展数据缓冲器中读出扩展数据。

5. 发明授权

US06609232B2 Logic compound method and logic compound apparatus 失效
标题翻译：逻辑复合法和逻辑复合器
公开(公告)号：US06609232B2
公开(公告)日：2003-08-19
申请号：US09791818
申请日：2001-02-26
申请人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
发明人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.
摘要翻译：在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

6. 发明授权

US06792583B1 Information processing apparatus, information processing system, and storage media 失效
标题翻译：信息处理装置，信息处理系统和存储介质
公开(公告)号：US06792583B1
公开(公告)日：2004-09-14
申请号：US09501977
申请日：2000-02-11
申请人： Yoshitaka Takahashi , Kotaro Shimamura , Takashi Hotta , Teppei Hirotsu , Katsuichi Tomobe
发明人： Yoshitaka Takahashi , Kotaro Shimamura , Takashi Hotta , Teppei Hirotsu , Katsuichi Tomobe
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.
摘要翻译：在信息处理装置中，不知道LSI的设计者的用户在不降低LSI的性能的情况下修改LSI的布局图。设计LSI的设计者使用电路设计装置来存储包括构成LSI的每个块的功能的电路信息，关于块的分配的平面布置图以及作为设计者的专有技术的评估指标，与彼此。用户使用平面图修改装置来修改平面布置图并根据评价指标来评估修改的平面图。

7. 发明授权

US07752527B2 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

8. 发明授权

US08095825B2 Error correction method with instruction level rollback 有权
标题翻译：具有指令级回滚的纠错方法
公开(公告)号：US08095825B2
公开(公告)日：2012-01-10
申请号：US11623441
申请日：2007-01-16
申请人： Teppei Hirotsu , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei Hirotsu , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，寄存器文件的内容由延迟的寄存器文件恢复，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

9. 发明授权

US08578135B2 Apparatus for calculating and prefetching a branch target address 有权
标题翻译：用于计算和预取分支目标地址的装置
公开(公告)号：US08578135B2
公开(公告)日：2013-11-05
申请号：US13423145
申请日：2012-03-16
申请人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
发明人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

10. 发明申请

US20050172110A1 Information processing apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20050172110A1
公开(公告)日：2005-08-04
申请号：US11046453
申请日：2005-01-28
申请人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
发明人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

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