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1. 发明授权

US6025275A Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect 失效
标题翻译：形成改进的厚镀铜铜互连和相关辅助金属互连的方法
公开(公告)号：US6025275A
公开(公告)日：2000-02-15
申请号：US991997
申请日：1997-12-17
申请人： Taylor R. Efland , Quang X. Mai , Charles E. Williams , Stephen A. Keller
发明人： Taylor R. Efland , Quang X. Mai , Charles E. Williams , Stephen A. Keller
IPC分类号： H01L21/768 , H01L23/532 , H01L21/302
CPC分类号： H01L21/76802 , H01L23/53238 , H01L2924/0002
摘要： A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).
摘要翻译：可以通过在半导体层（12）上形成金属层（20）来制造厚电镀互连（80）。介电层（22）可以形成在金属层（20）上。可以在电介质层（22）中形成通孔（24）以暴露金属层（20）。铜导线（50）可以通过电介质层（22）的通孔（24）形成为电耦合到金属层（20）。阻挡构件（88）可以形成在铜引线（50）上。包含铝的可粘合构件（86）可以形成在阻挡构件（88）上。

2. 发明授权

US6020640A Thick plated interconnect and associated auxillary interconnect 失效
标题翻译：厚电镀互连和相关辅助互连
公开(公告)号：US6020640A
公开(公告)日：2000-02-01
申请号：US992282
申请日：1997-12-17
申请人： Taylor R. Efland , Quang X. Mai , Charles E. Williams , Stephen A. Keller
发明人： Taylor R. Efland , Quang X. Mai , Charles E. Williams , Stephen A. Keller
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/485 , H01L23/52 , H01L23/532 , H01L23/48 , H01L29/40
CPC分类号： H01L24/10 , H01L23/53233 , H01L23/53238 , H01L24/13 , H01L2224/0401 , H01L2224/05018 , H01L2224/05558 , H01L2224/0558 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181
摘要： A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).
摘要翻译：包括铜引线（50）和耦合到铜引线（50）的接合盖（84）的厚电镀互连（80）。接合盖（84）可以包括由包含铝的可结合层（62）形成的可结合构件（86）。阻挡构件（88）可以由阻挡层（60）形成。阻挡构件（88）可以设置在可结合构件（86）和铜导线（50）之间。

3. 发明授权

US06683380B2 Integrated circuit with bonding layer over active circuitry 有权
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US06683380B2
公开(公告)日：2004-01-27
申请号：US10191453
申请日：2002-07-10
申请人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
发明人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05644 , H01L2224/05664 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/4847 , H01L2224/48644 , H01L2224/48664 , H01L2224/48764 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/4945 , H01L2224/85191 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A-2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

4. 发明授权

US06140702A Plastic encapsulation for integrated circuits having plated copper top surface level interconnect 失效
标题翻译：具有电镀铜顶表面级互连的集成电路的塑料封装
公开(公告)号：US06140702A
公开(公告)日：2000-10-31
申请号：US864386
申请日：1997-05-28
申请人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
发明人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05647 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48647 , H01L2224/48747 , H01L2224/48847 , H01L2224/73265 , H01L24/45 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/181
摘要： A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.
摘要翻译：一种塑料封装集成电路（20），其具有厚镀铜的顶表面级互连结构。半导体集成电路（20）在半导体衬底（23）的表面形成有器件。第一和第二金属化层（27,31）形成在衬底上并且接触选定的所述器件。金属化的第一和第二层可以通过通孔彼此接触。然后在第二金属层（31）上形成厚的顶表面级金属互连层（35），或者物理地接触第二金属层或选择性地电接触它。表面金属（35）由高导电性铜层制成。厚表面金属层（35）基本上降低了器件（20）的互连金属化的电阻，并且进一步消除了现有技术的集成电路所经历的电流去差和早期故障定位问题。在一个实施例中，铜表面水平互连层（35）涂覆有可以接收接合线的材料（37）的薄阻挡层。然后将整个结构封装在塑料封装（22）中，使得塑料与铜互连金属（35）物理接触。与铜互连金属（35）物理接触的塑料封装（22）的使用消除了对现有技术的钝化层的需要。描述其他设备和方法。

5. 发明授权

US6140150A Plastic encapsulation for integrated circuits having plated copper top surface level interconnect 有权
公开(公告)号：US6140150A
公开(公告)日：2000-10-31
申请号：US291884
申请日：1999-04-14
申请人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
发明人： Taylor R. Efland , Dale J. Skelton , Quang X. Mai , Charles E. Williams
IPC分类号： H01L23/482 , H01L23/485 , H01L23/532 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/05 , H01L23/4827 , H01L23/53238 , H01L24/48 , H01L2224/04042 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48747 , H01L2224/48755 , H01L2224/48764 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L24/45 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要： A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.

6. 发明授权

US5905308A Bond pad for integrated circuit 失效
标题翻译：集成电路用焊盘
公开(公告)号：US5905308A
公开(公告)日：1999-05-18
申请号：US964517
申请日：1997-11-05
申请人： Taylor R. Efland , Charles E. Williams , Buford H. Carter
发明人： Taylor R. Efland , Charles E. Williams , Buford H. Carter
IPC分类号： H01L21/60 , H01L23/485 , A01L23/48 , A01L23/52
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48458 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/85205 , H01L24/45 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19043 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076
摘要： A bond pad (18, 58) may comprise a base (20, 60) of bondable material. The base (20, 60) may have a periphery (26, 66). A segment of an interconnect (24, 64) may contact an extended section (28, 68) of the periphery (26, 66) to electrically couple the interconnect (24, 64) to the bond pad (18,58). The interconnect (24, 64) may comprise a material less resistive than the bondable material.
摘要翻译：接合焊盘（18,58）可以包括可结合材料的基部（20,60）。基座（20,60）可以具有周边（26,66）。互连部分（24,64）可以接触周边（26,66）的延伸部分（28,68）以将互连（24,64）电耦合到接合焊盘（18,58）。互连（24,64）可以包括比可结合材料更小的电阻的材料。

7. 再颁专利

USRE35259E High humidity steam cooker with continuously running conveyor 失效
公开(公告)号：USRE35259E
公开(公告)日：1996-06-04
申请号：US541537
申请日：1990-06-21
申请人： Charles E. Williams
发明人： Charles E. Williams
IPC分类号： A23B4/005 , A23L3/06 , A23L3/18 , A47J27/16 , A47J37/04
CPC分类号： A47J27/16 , A23B4/0053 , A23L3/06 , A23L3/185 , A47J37/044 , Y02P60/85
摘要： A steam cooker processes large quantities of food products such as meat, fish, poultry and produce passed therethrough in a spiral conveyor path. The continuously running conveyor is provided with loading and unloading stations outside the cooker and with a continuously operable spray detergent cleaning bath.Efficient cooking is achieved without loss of humidity, flavor or appearance by maintaining water drop free steam at near 100.degree. C. and 100% humidity at a pressure greater than atmospheric and by features of the apparatus including control of steam flow out of the cooking chamber and introduction of cold air thereinto.Two separate steam sources, internal and external, are provided with the internal source comprising a heated pool of water on the floor of the cooker chamber, which is agitated for heat transfer efficiency and to remove fat or drippings from the cooking products.Sanitation means include mounting of machinery parts outside the cooker, access to all sides of the cooking chamber for cleaning, an internal cleaning spray system and other apparatus features.

8. 发明授权

US5406676A Multi-directional carrier system for operable partitions 失效
标题翻译：用于可操作分区的多向载波系统
公开(公告)号：US5406676A
公开(公告)日：1995-04-18
申请号：US46122
申请日：1993-04-09
申请人： Charles E. Williams
发明人： Charles E. Williams
IPC分类号： E05D15/00 , E05D15/06 , E05D15/36 , E06B3/92 , F16C29/04
CPC分类号： E05D15/0626 , E05D15/0613 , E06B3/924 , F16C29/045 , F16C29/048 , E05Y2201/692 , E05Y2800/21 , E05Y2900/142 , Y10T16/35 , Y10T16/376
摘要： A multi-directional carrier includes a track and first and second ledges on the track. The ledges are relatively spaced vertically and horizontally. First and second discs are supported on a bolt in vertical spaced relation. One of the discs engages one of the ledges on one side of the bolt and the other disc engages the other ledge on the other side of the bolt. The underside of each disc has an angled surface and the upper side of each of the ledges has a complementary angled surface which is engaged by one of the disc angled surfaces. The angles of both said disc and ledge surfaces are substantially equal, being in the range of 2.degree. to 8.degree. to the horizontal, specifically 5.degree.. The discs can be made of metal and the underside of each disc can also be provided with rings of suitable bearing material engaging the ledges.
摘要翻译：多方向载体包括轨道和轨道上的第一和第二凸缘。这些凸缘在垂直和水平方向上相对间隔开。第一和第二盘以垂直间隔的关系支撑在螺栓上。其中一个圆盘与螺栓一侧的一个凸缘接合，另一个圆盘与螺栓另一侧的另一个凸缘啮合。每个盘的下侧具有成角度的表面，并且每个突出部的上侧具有互补的成角度的表面，该表面由盘倾斜表面中的一个接合。所述盘和凸缘表面的角度基本上相等，在水平2度至8度的范围内，特别是5度。盘可以由金属制成，并且每个盘的下侧还可以设置有与凸缘接合的合适的轴承材料的环。

9. 发明授权

US4903120A Chip carrier with interconnects on lid 失效
标题翻译：带盖的互连芯片载体
公开(公告)号：US4903120A
公开(公告)日：1990-02-20
申请号：US801177
申请日：1985-11-22
申请人： Gary L. Beene , Thomas D. Petrovich , Charles E. Williams
发明人： Gary L. Beene , Thomas D. Petrovich , Charles E. Williams
IPC分类号： H01L21/60 , H01L23/04 , H01L23/057 , H01L23/12 , H01L23/498 , H01L25/04 , H01L25/18
CPC分类号： H01L23/49827 , H01L23/04 , H01L23/057 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/14
摘要： A chip carrier with multiple through hole vias in its hermetic sealing lid. One or more chips is mounted on the inner surface of that lid. The lid contains multiple through vias, and the semiconductor chip on the inner surface of the lid is bonded to the vias in the lid by TAB strips or (optionally) by wire bonds. The vias in the lid connect these leads through to contacts on the outer surface of the package. These contacts can than be connected to (using interconnect structures such as TAB strips, or printed wiring boards, or discretionary wiring), to provide circuit interconnection. Preferably low-power-dissipation chips are mounted on the inner surface of the lid in this fashion, with higher-power-dissipation chips mounted on the bottom surface of the chip cavity.
摘要翻译：在其密封盖中具有多个通孔通孔的芯片载体。一个或多个芯片安装在该盖的内表面上。盖子包含多个通孔，盖子的内表面上的半导体芯片通过TAB条或（可选地）通过引线键合到盖子中的通孔上。盖子中的通孔将这些引线连接到包装外表面上的触点。这些触点可以连接到（使用诸如TAB条或印刷电路板之间的互连结构或任意布线），以提供电路互连。优选地，以这种方式将低功耗芯片安装在盖的内表面上，其中较高功率耗散的芯片安装在芯片腔的底表面上。

10. 外观设计

USD293810S Fishing lure 失效
公开(公告)号：USD293810S
公开(公告)日：1988-01-19
申请号：US757672
申请日：1985-07-22
申请人： Loren G. Hill , Charles E. Williams
设计人： Loren G. Hill , Charles E. Williams

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