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1. 发明授权

US06683380B2 Integrated circuit with bonding layer over active circuitry 有权
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US06683380B2
公开(公告)日：2004-01-27
申请号：US10191453
申请日：2002-07-10
申请人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
发明人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05644 , H01L2224/05664 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/4847 , H01L2224/48644 , H01L2224/48664 , H01L2224/48764 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/4945 , H01L2224/85191 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A-2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

2. 发明授权

US6144100A Integrated circuit with bonding layer over active circuitry 失效
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US6144100A
公开(公告)日：2000-11-07
申请号：US959410
申请日：1997-10-28
申请人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
发明人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
IPC分类号： H01L23/485 , H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/45124 , H01L2224/45144 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48744 , H01L2224/48755 , H01L2224/48764 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3025
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A 2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

3. 发明授权

US08436601B2 DC-DC converter with automatic inductor detection for efficiency optimization 有权
标题翻译：具有自动电感检测功能的DC-DC转换器进行效率优化
公开(公告)号：US08436601B2
公开(公告)日：2013-05-07
申请号：US13028034
申请日：2011-02-15
申请人： Gerhard Thiele , Konrad Wagensohner , Josy Bernard
发明人： Gerhard Thiele , Konrad Wagensohner , Josy Bernard
IPC分类号： G05F1/575 , G05F1/618
CPC分类号： H02M3/156 , H02M2001/0009
摘要： A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator compares the output voltage with a reference voltage. A detector detects when inductor current approaches zero. A timer is configured to determine a minimum ON time of the high-side power transistor optimized for a particular value inductor. A current detector detects current flow in the back-gate diode of the low-side power transistor. timer is configured to determine an overriding ON time in response to the back-gate current detector. Logic provides control signals to gate power transistors in response to the comparator and the longer one of the minimum ON time and the overriding ON time. The minimum ON time for the high-side power transistor is adjusted in response to the actual inductance of the inductor.
摘要翻译： DC-DC转换器具有串联连接在电源端子之间的高侧功率和低侧功率晶体管，连接在功率晶体管和输出端子之间的电感器。比较器将输出电压与参考电压进行比较。检测器检测电感电流何时接近零。定时器被配置为确定针对特定值电感器优化的高侧功率晶体管的最小导通时间。电流检测器检测低边功率晶体管的背栅极二极管中的电流。定时器被配置为响应于背栅极电流检测器确定覆盖ON时间。逻辑提供响应于比较器的栅极功率晶体管的控制信号和最小导通时间和覆盖导通时间中较长的一个。响应于电感器的实际电感，调整高侧功率晶体管的最小导通时间。

4. 发明授权

US08928299B2 Low power switching DC-DC converter and method of the same 有权
标题翻译：低功率开关DC-DC转换器及其方法相同
公开(公告)号：US08928299B2
公开(公告)日：2015-01-06
申请号：US13481541
申请日：2012-05-25
申请人： Markus Matzberger , Konrad Wagensohner , Erich Bayer
发明人： Markus Matzberger , Konrad Wagensohner , Erich Bayer
IPC分类号： G05F3/08 , H02M3/158 , H02M1/00
CPC分类号： H02M3/1588 , H02M3/158 , H02M2001/0009 , Y02B70/1466
摘要： A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.
摘要翻译：低功率DC-DC转换器包括耦合到输入节点的转换器级，并且具有低侧开关和整流器开关。峰值电流检测器感测低侧开关处的电流，零电流检测器感测整流器开关处的电流。如果峰值电流检测器检测到预定的峰值电流，则将低侧开关设置为非导通状态，并且整流器切换到导通状态。如果零电流检测器在整流器开关处检测到零电流，则其被配置为将整流器开关设置为非导通状态。后续电流峰值之间的时间间隔由电荷比较器触发，该电荷比较器接收馈送到低侧的平均电流，并且从输入节点接收整流器开关，以及通过参考电流源耦合到电荷比较器的参考电流。

5. 发明申请

US20130314067A1 LOW POWER DC-DC CONVERTER AND METHOD OF OPERATING THE SAME 有权
标题翻译：低功率DC-DC转换器及其操作方法
公开(公告)号：US20130314067A1
公开(公告)日：2013-11-28
申请号：US13481541
申请日：2012-05-25
申请人： Markus Matzberger , Konrad Wagensohner , Erich Bayer
发明人： Markus Matzberger , Konrad Wagensohner , Erich Bayer
IPC分类号： G05F3/08
CPC分类号： H02M3/1588 , H02M3/158 , H02M2001/0009 , Y02B70/1466
摘要： A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.
摘要翻译：低功率DC-DC转换器包括耦合到输入节点的转换器级，并且具有低侧开关和整流器开关。峰值电流检测器感测低侧开关处的电流，零电流检测器感测整流器开关处的电流。如果峰值电流检测器检测到预定的峰值电流，则将低侧开关设置为非导通状态，并且整流器切换到导通状态。如果零电流检测器在整流器开关处检测到零电流，则其被配置为将整流器开关设置为非导通状态。后续电流峰值之间的时间间隔由电荷比较器触发，该电荷比较器接收馈送到低侧的平均电流，并且从输入节点接收整流器开关，以及通过参考电流源耦合到电荷比较器的参考电流。

6. 发明申请

US20080136457A1 SERIAL INTEFACE CIRCUIT FOR A SINGLE LOGIC INPUT PIN OF AN ELECTRONIC SYSTEM 有权
标题翻译：用于电子系统的单个逻辑输入引脚的串行接口电路
公开(公告)号：US20080136457A1
公开(公告)日：2008-06-12
申请号：US11876207
申请日：2007-10-22
申请人： Konrad Wagensohner , Anton Winkler , Markus Matzberger
发明人： Konrad Wagensohner , Anton Winkler , Markus Matzberger
IPC分类号： G01R29/02
CPC分类号： H03M5/08
摘要： A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of the input signal. The edge detection circuit is connected to the up/down counter to start up counting from a reset value upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction. The decoder further comprises a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.
摘要翻译：一种用于电子系统的单个逻辑输入引脚的串行接口电路，包括用于将施加到引脚的脉宽调制输入信号转换成逻辑低和逻辑高值的序列的解码器。解码器包括具有连接到时钟源的计数输入的上/下计数器，边缘检测电路检测输入信号的上升沿和下降沿。边缘检测电路连接到上/下计数器，以在检测到第一方向上的边缘时从复位值开始计数，并且在沿第二方向检测到边缘时从当前计数开始计数。解码器还包括位值决定电路，当检测到第二方向上的边缘时，当上/下计数器的计数高于复位值时，传递第一逻辑值，并且当上升计数时，递送第二逻辑值 /递减计数器在检测到第二方向上的边缘时处于或低于复位值。

7. 发明授权

US5841297A Circuit arrangement for driving an MOS field-effect transistor allocated to the supply circuit of an electrical load 失效
标题翻译：用于驱动分配给电负载的电源电路的MOS场效应晶体管的电路装置
公开(公告)号：US5841297A
公开(公告)日：1998-11-24
申请号：US684900
申请日：1996-07-25
申请人： Erich Bayer , Konrad Wagensohner
发明人： Erich Bayer , Konrad Wagensohner
IPC分类号： H03K17/0412 , H03K17/16 , H03K17/687 , H03K19/00 , H03K19/0175 , H03K3/01
CPC分类号： H03K17/163 , H03K17/04123
摘要： A circuit arrangement 10 for driving an MOS field-effect transistor QO allocated to the supply circuit KO of an electrical load R.sub.L contains a charging circuit K1 and a discharging circuit K2, which can be alternatively connected to the MOS field-effect transistor QO. A sensing circuit K3 supplies the measuring signal S.sub.M typical of gate-source voltage U.sub.GS of the MOS field-effect transistor QO, via which the internal resistance of the charging or discharging circuit K1, K2 and/or a current I.sub.a impressed upon these circuits K1, K2, in the sense of a positive feedback, is controlled, in such a way that the resulting time constant, according to which the input capacitance of the MOS field-effect, transistor QO is charged or discharged, becomes smaller during the transition of the MOS field-effect transistor QO from the off state to the conductive state and larger during the transition from the conductive to the off-state.
摘要翻译：用于驱动分配给电负载RL的电源电路KO的MOS场效应晶体管QO的电路装置10包括充电电路K1和可以替代地连接到MOS场效应晶体管QO的放电电路K2。感测电路K3提供典型的MOS场效应晶体管QO的栅极 - 源极电压UGS的测量信号SM，通过该测量信号SM将充电或放电电路K1，K2的内部电阻和/或施加在这些电路K1上的电流Ia 在正反馈意义上的K2被控制，使得在MOS场效应晶体管QO的输入电容被充电或放电的结果时间常数在转换期间变得更小 MOS场效应晶体管QO从断开状态到导通状态，并且在从导通状态转换到断开状态期间较大。

8. 发明申请

US20110204860A1 DC-DC CONVERTER WITH AUTOMATIC INDUCTOR DETECTION FOR EFFICIENCY OPTIMIZATION 有权
标题翻译：具有自动电感检测功能的DC-DC转换器，用于高效优化
公开(公告)号：US20110204860A1
公开(公告)日：2011-08-25
申请号：US13028034
申请日：2011-02-15
申请人： Gerhard Thiele , Konrad Wagensohner , Josy Bernard
发明人： Gerhard Thiele , Konrad Wagensohner , Josy Bernard
IPC分类号： G05F1/10
CPC分类号： H02M3/156 , H02M2001/0009
摘要： A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator compares the output voltage with a reference voltage. A detector detects when inductor current approaches zero. A timer is configured to determine a minimum ON time of the high-side power transistor optimized for a particular value inductor. A current detector detects current flow in the back-gate diode of the low-side power transistor. timer is configured to determine an overriding ON time in response to the back-gate current detector. Logic provides control signals to gate power transistors in response to the comparator and the longer one of the minimum ON time and the overriding ON time. The minimum ON time for the high-side power transistor is adjusted in response to the actual inductance of the inductor.
摘要翻译： DC-DC转换器具有串联连接在电源端子之间的高侧功率和低侧功率晶体管，连接在功率晶体管和输出端子之间的电感器。比较器将输出电压与参考电压进行比较。检测器检测电感电流何时接近零。定时器被配置为确定针对特定值电感器优化的高侧功率晶体管的最小导通时间。电流检测器检测低边功率晶体管的背栅极二极管中的电流。定时器被配置为响应于背栅极电流检测器确定覆盖ON时间。逻辑提供响应于比较器的栅极功率晶体管的控制信号和最小导通时间和覆盖导通时间中较长的一个。响应于电感器的实际电感，调整高侧功率晶体管的最小导通时间。

9. 发明申请

US20100165686A1 RECTIFIER CIRCUIT 审中-公开
标题翻译：整流器电路
公开(公告)号：US20100165686A1
公开(公告)日：2010-07-01
申请号：US12643003
申请日：2009-12-21
申请人： Markus Matzberger , Konrad Wagensohner , Erich-Johann Bayer
发明人： Markus Matzberger , Konrad Wagensohner , Erich-Johann Bayer
IPC分类号： H02M7/12
CPC分类号： H02M7/219 , Y02B70/1408
摘要： A rectifier circuit for use in an energy harvesting application in which mechanical energy is converted into electrical energy by using an AC generator using an active rectifier bridge with a pair of input terminals adapted to be connected to an output of the AC generator and a pair of output terminals, an inductor connected across the output terminals of the active rectifier bridge and a storage capacitor. A pair of output switches selectively connects the storage capacitor across the inductor. A controller controls the active rectifier bridge and the pair of output switches such that in successive switching cycles within any half wave of AC input voltage from the output of the AC generator the inductor is first loaded by current from the output of the AC generator and then discharged into the storage capacitor. An energy harvesting system which uses an AC generator for generating electrical energy out of mechanical energy, a rectifier circuit which is connected with the input to the output of the AC generator and a low power wireless system as application unit. A method of rectifying an AC output voltage of an AC generator for use in an energy harvesting application.
摘要翻译：一种用于能量收集应用中的整流器电路，其中机械能通过使用具有适于连接到AC发电机的输出的一对输入端的有源整流桥使用交流发电机转换成电能，并且一对输出端子，连接在有源整流器桥的输出端子和存储电容器之间的电感器。一对输出开关选择性地将存储电容器连接在电感器两端。控制器控制有源整流桥和一对输出开关，使得在来自交流发电机的输出端的任何一半的交流输入电压的连续开关周期内，电感器首先通过电流从交流发电机的输出负载，然后放入存储电容器。一种使用AC发电机从机械能产生电能的能量收集系统，与AC发电机的输出端连接的整流电路和作为应用单元的低功率无线系统。一种整流用于能量采集应用中的交流发电机的交流输出电压的方法。

10. 发明授权

US07474234B2 Serial interface circuit for a single logic input pin of an electronic system 有权
标题翻译：用于电子系统的单个逻辑输入引脚的串行接口电路
公开(公告)号：US07474234B2
公开(公告)日：2009-01-06
申请号：US11876207
申请日：2007-10-22
申请人： Konrad Wagensohner , Anton Winkler , Markus Matzberger
发明人： Konrad Wagensohner , Anton Winkler , Markus Matzberger
IPC分类号： H03M5/08
CPC分类号： H03M5/08
摘要： A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of the input signal. The edge detection circuit is connected to the up/down counter to start up counting from a reset value upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction. The decoder further comprises a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.
摘要翻译：一种用于电子系统的单个逻辑输入引脚的串行接口电路，包括用于将施加到引脚的脉宽调制输入信号转换成逻辑低和逻辑高值的序列的解码器。解码器包括具有连接到时钟源的计数输入的上/下计数器，边缘检测电路检测输入信号的上升沿和下降沿。边缘检测电路连接到上/下计数器，以在检测到第一方向上的边缘时从复位值开始计数，并且在沿第二方向检测到边缘时从当前计数开始计数。解码器还包括位值决定电路，当检测到第二方向上的边缘时，当上/下计数器的计数高于复位值时，传递第一逻辑值，并且当上升计数时，递送第二逻辑值 /递减计数器在检测到第二方向上的边缘时处于或低于复位值。

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