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1. 发明授权

US06664122B1 Electroless copper deposition method for preparing copper seed layers 有权
标题翻译：用于制备铜籽晶层的无电铜沉积方法
公开(公告)号：US06664122B1
公开(公告)日：2003-12-16
申请号：US09996425
申请日：2001-11-27
申请人： Tatyana N. Andryuschenko , Jonathan D. Reid , Steven T. Mayer , Eric G. Webb
发明人： Tatyana N. Andryuschenko , Jonathan D. Reid , Steven T. Mayer , Eric G. Webb
IPC分类号： H01L2166
CPC分类号： H01L21/76843 , C23C18/1617 , C23C18/1669 , C23C18/1675 , C23C18/1676 , C23C18/168 , C23C18/1692 , C23C18/40 , H01L21/288 , H01L21/76864 , H01L21/76868 , H01L21/76873 , H01L2221/1089 , Y10S977/89
摘要： Disclosed is a procedure for deposition of a thin and relatively continuous electroless copper film on the substrate of sub-micron integrated circuit features. The electroless copper film is deposited onto a previously deposited PVD copper film, which may be discontinuous. The continuous film formed by electroless deposition allows for sufficient filling of the sub-micron integrated circuit features by electrodeposition. The electroless bath employed to form the continuous electroless copper film may be composed of a reducing agent, a complexing agent, a source of copper ions, a pH adjuster, and optionally one or more surfactants and/or stabilizers. In one example, the reducing agent contains an aldehyde moiety.
摘要翻译：公开了在亚微米集成电路特征的衬底上沉积薄而相对连续的无电铜膜的步骤。将化学镀铜膜沉积在预先沉积的PVD铜膜上，其可以是不连续的。通过无电沉积形成的连续膜允许通过电沉积充分填充亚微米集成电路特征。用于形成连续化学镀铜膜的无电镀浴可以由还原剂，络合剂，铜离子源，pH调节剂和任选的一种或多种表面活性剂和/或稳定剂组成。在一个实例中，还原剂含有醛部分。

2. 发明授权

US08043958B1 Capping before barrier-removal IC fabrication method 有权
标题翻译：阻隔去除IC封装制造方法
公开(公告)号：US08043958B1
公开(公告)日：2011-10-25
申请号：US12875857
申请日：2010-09-03
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译：在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。

3. 发明授权

US07811925B1 Capping before barrier-removal IC fabrication method 有权
标题翻译：阻隔去除IC封装制造方法
公开(公告)号：US07811925B1
公开(公告)日：2010-10-12
申请号：US12184145
申请日：2008-07-31
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译：在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。

4. 发明授权

US07605082B1 Capping before barrier-removal IC fabrication method 有权
标题翻译：阻隔去除IC封装制造方法
公开(公告)号：US07605082B1
公开(公告)日：2009-10-20
申请号：US11251353
申请日：2005-10-13
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/44
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译：在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。

5. 发明授权

US08415261B1 Capping before barrier-removal IC fabrication method 有权
公开(公告)号：US08415261B1
公开(公告)日：2013-04-09
申请号：US13270809
申请日：2011-10-11
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/00 , B01J19/12
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

6. 发明授权

US09109295B2 Electrolyte concentration control system for high rate electroplating 有权
标题翻译：高速电镀电解质浓度控制系统
公开(公告)号：US09109295B2
公开(公告)日：2015-08-18
申请号：US12577619
申请日：2009-10-12
申请人： Jonathan D. Reid , Seshasayee Varadarajan , Steven T. Mayer
发明人： Jonathan D. Reid , Seshasayee Varadarajan , Steven T. Mayer
IPC分类号： C25D17/00 , C25D21/18 , C25D3/38 , C25D21/02 , C25D21/14 , C25D7/12
CPC分类号： C25D17/00 , C25D3/38 , C25D7/123 , C25D17/001 , C25D21/02 , C25D21/14 , C25D21/18
摘要： An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.
摘要翻译：用于在半导体衬底上填充凹陷特征的电镀设备包括电解质浓缩器，其被配置用于浓缩具有Cu 2+离子的电解质，以形成在20℃下已经过饱和的浓缩电解质溶液。电解质保持在高于 20℃，例如至少约40℃。该设备还包括浓缩电解质储存器和电镀池，其中电镀单元被配置为在至少约40℃的温度下用浓缩电解质电镀。在至少约40℃的温度下，具有Cu2 +浓度至少约60g / L的电解质的电镀导致非常快的铜沉积速率，并且特别适合于填充大的高纵横比特征，例如通过硅通孔。

7. 发明授权

US08513124B1 Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers 有权
标题翻译：铜电镀工艺，用于跨晶片沉积均匀并在半贵金属涂覆的晶片上无空隙填充
公开(公告)号：US08513124B1
公开(公告)日：2013-08-20
申请号：US12785205
申请日：2010-05-21
申请人： Thomas A. Ponnuswamy , John H. Sukamto , Jonathan D. Reid , Steven T. Mayer
发明人： Thomas A. Ponnuswamy , John H. Sukamto , Jonathan D. Reid , Steven T. Mayer
IPC分类号： H01L21/44
CPC分类号： H01L21/76873 , C25D3/38 , C25D5/18 , C25D5/50 , C25D7/123 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L2221/1089
摘要： Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.
摘要翻译：公开了一种沉积铜籽晶层的方法，该铜籽晶层用于随后电镀铜的体层。铜种子层可以以不同的工艺沉积，包括CVD，PVD和电镀。利用用于沉积铜籽晶层的电镀方法，公开了用于沉积铜合金晶种层的方法，用非腐蚀性电解质在半贵金属层上沉积铜籽晶层的方法，处理半贵金属的方法沉积铜籽晶层的层，以及用于促进越过半导体晶片的更均匀的铜籽晶层沉积的方法。

8. 发明授权

US07622024B1 High resistance ionic current source 有权
标题翻译：高电阻离子电流源
公开(公告)号：US07622024B1
公开(公告)日：2009-11-24
申请号：US11040359
申请日：2005-01-20
申请人： Steven T. Mayer , Jonathan D. Reid
发明人： Steven T. Mayer , Jonathan D. Reid
IPC分类号： C25D17/00 , C25D5/00
CPC分类号： C25D17/12 , C25D7/123 , C25D17/001 , C25D17/008 , H01L21/2885 , Y10S204/07
摘要： A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.
摘要翻译：将基本上均匀的金属层电镀在其上具有种子层的工件上。这是通过使用“高电阻离子电流源”来实现的，其通过将高电阻膜（例如，微孔陶瓷或微波玻璃元件）放置在靠近晶片来解决端子问题，从而使系统的电阻变化。因此，膜近似于恒定电流源。通过保持晶片靠近膜表面，从膜顶部到表面的离子电阻远小于对晶片边缘的离子路径电阻，基本上补偿薄金属膜中的薄层电阻并引导附加电流在晶片的中心和中间。

9. 发明授权

US07097410B1 Methods and apparatus for controlled-angle wafer positioning 有权
标题翻译：受控角度晶片定位的方法和装置
公开(公告)号：US07097410B1
公开(公告)日：2006-08-29
申请号：US10379858
申请日：2003-03-04
申请人： Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind , Richard S. Hill
发明人： Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind , Richard S. Hill
IPC分类号： B65G47/90 , C25D5/00
CPC分类号： H01L21/2885 , C25D17/001 , Y10S414/135 , Y10S414/136
摘要： The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.
摘要翻译：在电镀过程中控制晶片相对于电解质表面的取向。将晶片沿着垂直于电解质表面的轨迹输送到电解质浴中。沿着该轨迹，晶片在进入电解质之前是成角度的，用于倾斜的浸入。根据给定情况下的最佳选择，晶圆可以以倾斜的方向进行电镀。此外，在一些设计中，晶片的取向可以在浸入期间或在电镀期间被主动调节，从而在各种电镀场景中提供灵活性。

10. 发明授权

US06821407B1 Anode and anode chamber for copper electroplating 有权
标题翻译：用于铜电镀的阳极和阳极室
公开(公告)号：US06821407B1
公开(公告)日：2004-11-23
申请号：US10231147
申请日：2002-08-27
申请人： Jonathan D. Reid , Timothy Mark Archer , Thomas Tan Vu , Seshasayee Varadarajan , Jon Henri , Steven T. Mayer , David Sauer , Anita Kang , Gerald Feldewerth
发明人： Jonathan D. Reid , Timothy Mark Archer , Thomas Tan Vu , Seshasayee Varadarajan , Jon Henri , Steven T. Mayer , David Sauer , Anita Kang , Gerald Feldewerth
IPC分类号： C25D338
CPC分类号： C25D21/12 , C25D17/002 , C25D17/12 , C25F7/00 , H05K3/241
摘要： An electroplating system includes (a) a phosphorized anode having an average grain size of at least about 50 micrometers and (b) plating apparatus that separates the anode from the cathode and prevents most particles generated at the anode from passing to the cathode. The separation may be accomplished by interposing a microporous chemical transport barrier between the anode and cathode. The relatively few particles that are generated at the large grain phosphorized copper anode are prevented from passing into the cathode (wafer) chamber area and thereby causing a defect in the part.
摘要翻译：电镀系统包括（a）平均晶粒尺寸为至少约50微米的磷化阳极和（b）将阳极与阴极分离的电镀装置，并防止在阳极处产生的大多数颗粒通过阴极。分离可以通过在阳极和阴极之间插入微孔化学传输阻挡层来实现。在大晶粒磷化铜阳极处产生的相对较少的颗粒被阻止进入阴极（晶片）室区域，从而导致该部分的缺陷。

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