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1. 发明申请

US20050113951A1 Method for designing a manufacturing process, method for providing manufacturing process design and technology computer-aided design system 失效
标题翻译：设计制造过程的方法，提供制造工艺设计和技术计算机辅助设计系统的方法
公开(公告)号：US20050113951A1
公开(公告)日：2005-05-26
申请号：US10933439
申请日：2004-09-03
申请人： Tatsuo Akiyama , Masahiro Abe , Kenji Hirakawa , Shigeru Komatsu
发明人： Tatsuo Akiyama , Masahiro Abe , Kenji Hirakawa , Shigeru Komatsu
IPC分类号： H01L21/02 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5068
摘要： A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second manufacturing facilities based on difference between the second electrical characteristic and the simulation electrical characteristic.
摘要翻译：一种设计电子设备的制造方法的方法，包括使用第一制造设备制造的第一电子设备的商业制造工艺的第一特征，通过拟合制造工艺和电气特性模拟的仿真参数来校准技术计算机辅助设计系统，以及第一电子装置的第一电特性; 获得由第二制造设备制造的第二电子装置的试制制造过程的第二特征和第二电子装置的第二电特性; 通过将第二特征代入对应于试制造过程的制造过程模拟来计算第二电子装置的模拟电特性; 将第二电特性与仿真电特性进行比较; 并基于第二电特性和仿真电特性之间的差异，创建第二制造设备的商业制造过程的设计规范。

2. 发明授权

US07272460B2 Method for designing a manufacturing process, method for providing manufacturing process design and technology computer-aided design system 失效
标题翻译：设计制造过程的方法，提供制造工艺设计和技术计算机辅助设计系统的方法
公开(公告)号：US07272460B2
公开(公告)日：2007-09-18
申请号：US10933439
申请日：2004-09-03
申请人： Tatsuo Akiyama , Masahiro Abe , Kenji Hirakawa , Shigeru Komatsu
发明人： Tatsuo Akiyama , Masahiro Abe , Kenji Hirakawa , Shigeru Komatsu
IPC分类号： G06F19/00 , G06F17/00
CPC分类号： G06F17/5068
摘要： A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second manufacturing facilities based on difference between the second electrical characteristic and the simulation electrical characteristic.
摘要翻译：一种设计电子设备的制造方法的方法，包括使用第一制造设备制造的第一电子设备的商业制造工艺的第一特征，通过拟合制造工艺和电气特性模拟的仿真参数来校准技术计算机辅助设计系统，以及第一电子装置的第一电特性; 获得由第二制造设备制造的第二电子装置的试制制造过程的第二特征和第二电子装置的第二电特性; 通过将第二特征代入对应于试制造过程的制造过程模拟来计算第二电子装置的模拟电特性; 将第二电特性与仿真电特性进行比较; 并基于第二电特性和仿真电特性之间的差异，创建第二制造设备的商业制造过程的设计规范。

3. 发明申请

US20050095774A1 Semiconductor device manufacturing system and method for manufacturing semiconductor devices 失效
标题翻译：半导体器件制造系统和半导体器件的制造方法
公开(公告)号：US20050095774A1
公开(公告)日：2005-05-05
申请号：US10935430
申请日：2004-09-08
申请人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
发明人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
IPC分类号： H01L21/3065 , G05B19/418 , H01L21/00 , H01L21/02 , H01L21/31 , H01L21/316 , H01L21/331
CPC分类号： G05B19/4184 , G05B19/41885 , G05B2219/32368 , G05B2219/45031 , Y02P90/14 , Y02P90/22 , Y02P90/26 , Y02P90/265
摘要： The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
摘要翻译：本发明提供了一种在半导体器件制造系统中交错数据帧的解决方案，其中用于对其表面上的半导体衬底和薄膜中的任一个进行处理的处理装置; 用于诊断处理装置的状态的自诊断系统; 以及参数拟合装置，当已经确定了所述处理的半导体衬底的检查结果被确定为正确时，用于维持所述自我诊断系统的参数，并且当所述检查结果具有所述参数时，改变所述自我诊断系统的参数被确定为不正确。

4. 发明授权

US07702413B2 Semiconductor device manufacturing system and method for manufacturing semiconductor devices including calculating oxide film thickness using real time simulator 失效
标题翻译：半导体器件制造系统以及使用实时仿真器计算氧化膜厚度的半导体器件的制造方法
公开(公告)号：US07702413B2
公开(公告)日：2010-04-20
申请号：US10935430
申请日：2004-09-08
申请人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
发明人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
IPC分类号： G06F19/00
CPC分类号： G05B19/4184 , G05B19/41885 , G05B2219/32368 , G05B2219/45031 , Y02P90/14 , Y02P90/22 , Y02P90/26 , Y02P90/265
摘要： The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
摘要翻译：本发明提供了一种在半导体器件制造系统中交错数据帧的解决方案，其中用于对其表面上的半导体衬底和薄膜中的任一个进行处理的处理装置; 用于诊断处理装置的状态的自诊断系统; 以及参数拟合装置，当已经确定了所述处理的半导体衬底的检查结果被确定为正确时，用于维持所述自我诊断系统的参数，并且当所述检查结果具有所述参数时，改变所述自我诊断系统的参数被确定为不正确。

5. 发明授权

US07623937B2 Semiconductor device manufacturing system and method for manufacturing semiconductor devices including calculating oxide film thickness using real time simulator 有权
公开(公告)号：US07623937B2
公开(公告)日：2009-11-24
申请号：US10935430
申请日：2004-09-08
申请人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
发明人： Yukihiro Ushiku , Akira Ogawa , Hidenori Kakinuma , Shunji Shuto , Masahiro Abe , Tatsuo Akiyama , Shigeru Komatsu
IPC分类号： G06F19/00
摘要： The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.

6. 发明授权

US5643046A Polishing method and apparatus for detecting a polishing end point of a semiconductor wafer 失效
标题翻译：用于检测半导体晶片的抛光终点的抛光方法和装置
公开(公告)号：US5643046A
公开(公告)日：1997-07-01
申请号：US390529
申请日：1995-02-17
申请人： Ichiro Katakabe , Naoto Miyashita , Tatsuo Akiyama
发明人： Ichiro Katakabe , Naoto Miyashita , Tatsuo Akiyama
IPC分类号： B24B37/013 , B24B49/04 , H01L21/304 , B24B7/22 , B24B49/12
CPC分类号： B24B37/013 , B24B49/04
摘要： A polishing method and apparatus are provided for detecting the polishing end point of a semi-conductor wafer having a polishing film and a stopper film formed thereon. First driving means are provided having a first drive shaft for rotating a polishing plate and a polishing cloth thereon. Second driving means having a second rotatable drive shaft are also provided. Mounting means for mounting the semi-conductor wafer is adapted to be rotated by the second driving means for polishing the wafer. Energy supplying means for supplying prescribed energy to the semi-conductor wafer are also included. Finally, detecting means for detecting a polishing end point of the polishing film is included and detects a variation of the energy supplied to the semi-conductor wafer. Different types of energy can be utilized such as infrared light and a vibration wave.
摘要翻译：提供了一种抛光方法和装置，用于检测在其上形成有抛光膜和阻挡膜的半导体晶片的研磨终点。第一驱动装置设置有用于使研磨板和抛光布旋转的第一驱动轴。还提供具有第二可旋转驱动轴的第二驱动装置。用于安装半导体晶片的安装装置适于通过用于抛光晶片的第二驱动装置旋转。还包括用于向半导体晶片提供规定能量的能量供给装置。最后，包括用于检测抛光膜的抛光终点的检测装置，并且检测提供给半导体晶片的能量的变化。可以使用不同类型的能量，例如红外光和振动波。

7. 发明授权

US5374835A Field effect transistor using compound semiconductor 失效
标题翻译：使用化合物半导体的场效应晶体管
公开(公告)号：US5374835A
公开(公告)日：1994-12-20
申请号：US63654
申请日：1993-05-20
申请人： Kizashi Shimada , Mayumi Kamura , Tatsuo Akiyama
发明人： Kizashi Shimada , Mayumi Kamura , Tatsuo Akiyama
IPC分类号： H01L29/812 , H01L21/338 , H01L29/423 , H01L29/778 , H01L29/80 , H01L31/112
CPC分类号： H01L29/42316
摘要： A compound semiconductor device such as HEMTs (High Electron Mobility Transistors), metal semiconductor field effect transistors, and the like includes a compound semiconductor substrate having an active region, an insulating film provided over the semiconductor substrate, source and drain electrodes provided on the active region, and a gate electrode located between the source and drain electrodes. In the structure, the gate electrode has a lower electrode portion for providing a Schottky barrier contact with the active region through an opening of the insulating film, and an upper electrode portion provided on the insulating film to extend toward only the drain electrode.
摘要翻译：诸如HEMT（高电子迁移率晶体管），金属半导体场效应晶体管等的化合物半导体器件包括具有有源区的化合物半导体衬底，设置在半导体衬底上的绝缘膜，设置在有源区上的源极和漏极以及位于源极和漏极之间的栅电极。在该结构中，栅电极具有用于通过绝缘膜的开口与有源区提供肖特基势垒接触的下电极部分和设置在绝缘膜上以仅向漏电极延伸的上电极部分。

8. 发明授权

US4700455A Method of fabricating Schottky gate-type GaAs field effect transistor 失效
标题翻译：制造肖特基栅型GaAs场效应晶体管的方法
公开(公告)号：US4700455A
公开(公告)日：1987-10-20
申请号：US792825
申请日：1985-10-30
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/338 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L29/812
摘要： A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.
摘要翻译：一种制造半导体器件的方法，其中二极管的绝缘膜设置在栅电极的侧壁上。该二氧化硅膜用于通过离子注入来形成源极和漏极区域期间限定栅极区域的长度，并且相对于源极和漏极区域精确地定位栅电极。

9. 发明申请

US20140044377A1 SHOT IMAGE PROCESSING SYSTEM, SHOT IMAGE PROCESSING METHOD, MOBILE TERMINAL, AND INFORMATION PROCESSING APPARATUS 审中-公开
标题翻译：拍摄图像处理系统，拍摄图像处理方法，移动终端和信息处理设备
公开(公告)号：US20140044377A1
公开(公告)日：2014-02-13
申请号：US14112525
申请日：2012-03-07
申请人： Shoji Yachida , Daisuke Nishiwaki , Tatsuo Akiyama
发明人： Shoji Yachida , Daisuke Nishiwaki , Tatsuo Akiyama
IPC分类号： G06T7/00
CPC分类号： G06T7/00 , H04N1/00244 , H04N1/00408 , H04N1/00973 , H04N5/232 , H04N2201/0039 , H04N2201/0096
摘要： A shot image processing system (100) includes a mobile terminal (1) that shoots an image of a conversion target region containing a character and/or an image, and displays the shot image containing the conversion target region on a display unit; a server that receives the shot image from the mobile terminal (1), wherein the server (2) determines a specifying method for specifying a location of the conversion target region in the received shot image, and transmits the determined specifying method to the mobile terminal, and the mobile terminal (1) specifies the location of the conversion target region in the shot image based on the specifying method received from the server (2), converts the conversion target region specified in the shot image into a prescribed format, and displays a converted image obtained by the conversion on the display unit (16).
摘要翻译：拍摄图像处理系统（100）包括：拍摄包含字符和/或图像的转换目标区域的图像的移动终端（1），并将包含转换对象区域的拍摄图像显示在显示单元上; 从移动终端（1）接收拍摄图像的服务器，其中服务器（2）确定用于指定接收到的镜头图像中的转换目标区域的位置的指定方法，并将所确定的指定方法发送到移动终端，并且移动终端（1）基于从服务器（2）接收的指定方法来指定拍摄图像中的转换目标区域的位置，将拍摄图像中指定的转换目标区域转换为规定格式，并且显示通过在显示单元（16）上的转换获得的转换图像。

10. 发明授权

US5229323A Method for manufacturing a semiconductor device with Schottky electrodes 失效
标题翻译：制造具有肖特基电极的半导体器件的方法
公开(公告)号：US5229323A
公开(公告)日：1993-07-20
申请号：US846985
申请日：1992-03-09
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/263 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/2633 , H01L21/28581 , Y10S148/139 , Y10S148/14
摘要： A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
摘要翻译：制造具有肖特基电极的半导体器件的方法包括以下步骤：在溅射装置的溅射处理室中对GaAs衬底的表面进行溅射蚀刻工艺; 并通过溅射将肖特基电极材料沉积在衬底的表面上以在处理室中形成肖特基电极，而不将衬底暴露于大气中。

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