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1. 发明授权

US5285414A Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal 失效
标题翻译：具有根据写数据和列选择信号的值驱动数据线的晶体管的半导体存储器
公开(公告)号：US5285414A
公开(公告)日：1994-02-08
申请号：US765838
申请日：1991-09-26
申请人： Tatsumi Yamauchi , Masahiro Iwamura , Kazutaka Mori
发明人： Tatsumi Yamauchi , Masahiro Iwamura , Kazutaka Mori
IPC分类号： G11C7/12 , G11C11/419 , G11C11/40
CPC分类号： G11C7/12 , G11C11/419
摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.
摘要翻译：半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。写驱动器包括第一组的MOSFET和第二组的MOSFET。在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。另一方面，第二组的MOSFET通常处于OFF状态。此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平数据线到低电平。

2. 发明授权

US5657264A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5657264A
公开(公告)日：1997-08-12
申请号：US159256
申请日：1993-11-30
申请人： Tatsumi Yamauchi , Masahiro Iwamura , Kazutaka Mori
发明人： Tatsumi Yamauchi , Masahiro Iwamura , Kazutaka Mori
IPC分类号： G11C7/12 , G11C11/419 , G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.
摘要翻译：半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。写驱动器包括第一组的MOSFET和第二组的MOSFET。在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。另一方面，第二组的MOSFET通常处于OFF状态。此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平数据线到低电平。

3. 发明授权

US06467004B1 Pipelined semiconductor devices suitable for ultra large scale integration 失效
标题翻译：适用于超大规模集成的流水线半导体器件
公开(公告)号：US06467004B1
公开(公告)日：2002-10-15
申请号：US09477448
申请日：2000-01-04
申请人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
发明人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
IPC分类号： G06F938
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
摘要翻译：提供了一种高速，高性能流水线半导体器件，例如流水线数据处理设备和存储器件。在流水线操作中，功能电路单元和传输单元在每个流水线级周期被单独控制。两个功能电路单元之间的传输单元在考虑周期时间的同时被分成N个传输单元，并且每个划分的传输单元被分配一个流水线级周期。

4. 发明授权

US6029220A Pipelined semiconductor devices suitable for ultra large scale integration 失效
公开(公告)号：US6029220A
公开(公告)日：2000-02-22
申请号：US957914
申请日：1992-10-08
申请人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
发明人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

5. 发明授权

US5590361A Microprocessor having an effective BiCMOS extra multiple input complex logic circuit 失效
标题翻译：微处理器具有有效的BiCMOS多输入复数逻辑电路
公开(公告)号：US5590361A
公开(公告)日：1996-12-31
申请号：US364406
申请日：1994-12-23
申请人： Masahiro Iwamura , Tatsumi Yamauchi , Shigeya Tanaka , Kazutaka Mori
发明人： Masahiro Iwamura , Tatsumi Yamauchi , Shigeya Tanaka , Kazutaka Mori
IPC分类号： H01L21/8249 , G06F15/16 , G06F15/78 , H01L27/06 , H03K19/08 , G06F15/00
CPC分类号： G06F15/7846 , Y02B60/1225
摘要： An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.
摘要翻译：使用N（N> / = 2）个单元逻辑电路构造的微处理器中用于执行大量控制和算术运算的额外大量的输入复数逻辑电路，每个单元逻辑电路包括M（M> / = 1）输入CMOS逻辑电路和一个双极晶体管，由此各个输出被集成以响应于M×N个数字输入信号产生一个输出，以提供高速，高密度集成和低功耗微处理器。

6. 发明授权

US5787043A Semiconductor memory device having a redundancy capability 失效
标题翻译：具有冗余能力的半导体存储器件
公开(公告)号：US5787043A
公开(公告)日：1998-07-28
申请号：US394765
申请日：1995-02-27
申请人： Takashi Akioka , Yuji Yokoyama , Atsushi Hiraishi , Masahiro Iwamura , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Koichi Motohashi
发明人： Takashi Akioka , Yuji Yokoyama , Atsushi Hiraishi , Masahiro Iwamura , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Koichi Motohashi
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04 , G11C7/00
CPC分类号： G11C29/844
摘要： A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.
摘要翻译：提供了一种半导体器件，其包括通过将存储器分成多个块形成的存储器衬垫和布置在每个存储器块块处的电路布置，用于至少对该块内的缺陷存储器单元产生访问抑制信号。使用这种布置，增加了用于消除缺陷的冗余存储单元阵列的访问速度，从而获得能够进行高速操作的半导体存储器件。

7. 发明授权

US5675548A Semiconductor integrated circuit having logi gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5675548A
公开(公告)日：1997-10-07
申请号：US608605
申请日：1996-02-29
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

8. 发明授权

US5345421A High speed, low noise semiconductor storage device 失效
标题翻译：高速，低噪音的半导体存储设备
公开(公告)号：US5345421A
公开(公告)日：1994-09-06
申请号：US905745
申请日：1992-06-29
申请人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
发明人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
IPC分类号： G11C11/417 , G11C11/401 , G11C11/409 , H03K19/003 , H03K19/00
CPC分类号： H03K19/00361
摘要： A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.
摘要翻译：提供了一种高速和低噪声的宽位输出半导体存储器件，其中输出电路被分组成两组，并且两个输出电路组被如此控制以在彼此相反的电平的方向上切换。

9. 发明申请

US20060192534A1 Generating apparatus and motor control apparatus 有权
标题翻译：发电机和电机控制装置
公开(公告)号：US20060192534A1
公开(公告)日：2006-08-31
申请号：US11356075
申请日：2006-02-17
申请人： Tatsumi Yamauchi , Shinji Shirakawa , Masahiro Iwamura , Masamitsu Inaba , Keiichi Mashino , Keiji Kunii
发明人： Tatsumi Yamauchi , Shinji Shirakawa , Masahiro Iwamura , Masamitsu Inaba , Keiichi Mashino , Keiji Kunii
IPC分类号： H02H7/06 , H02P9/00 , H02P11/00
CPC分类号： H02P9/102 , H02P6/005 , H02P9/107 , H02P2101/45
摘要： A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.
摘要翻译：具有励磁线圈L的发电机和用于控制流过励磁线圈L的励磁电流的SW 1控制电路2.当发电机的发电操作结束时，开关1 SW 1断开以中断励磁流过励磁线圈L的电流和开关2 SW 2截止，使励磁线圈L的励磁电流保持在包括具有能够快速衰减励磁电流的电阻元件的电阻元件1的电流路径。

10. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

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