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    • 3. 发明授权
    • Delay circuit and voltage controlled oscillation circuit
    • 延迟电路和压控振荡电路
    • US08362844B2
    • 2013-01-29
    • US12974782
    • 2010-12-21
    • Fumio Nakano
    • Fumio Nakano
    • H03K3/03
    • H03L7/0995H03K2005/00039H03K2005/00202H03K2005/00208
    • A delay circuit includes a delay unit having a first and a second power supply terminals, a pair of differential signal input terminals and a pair of differential signal output terminals. The signals entered to the pair of differential signal input terminals are delayed and output at the pair of differential signal output terminals. The delay circuit also includes a current controller that exercises control to cause a current of a current source, controlled by a current control terminal, to flow through the first and second power supply terminals of the delay unit. The delay circuit also includes a voltage controller that exercises control to provide for a constant potential difference between the first and the second power supply terminals (FIG. 1).
    • 延迟电路包括具有第一和第二电源端子的延迟单元,一对差分信号输入端子和一对差分信号输出端子。 输入到该对差分信号输入端子的信号在差动信号输出端子对被延迟输出。 延迟电路还包括电流控制器,其进行控制以使由电流控制端子控制的电流源的电流流过延迟单元的第一和第二电源端子。 延迟电路还包括电压控制器,其进行控制以在第一和第二电源端子之间提供恒定的电位差(图1)。
    • 9. 发明授权
    • Buffer circuit
    • 缓冲电路
    • US06703864B2
    • 2004-03-09
    • US09728103
    • 2000-12-01
    • Junichi TakeuchiFumio Nakano
    • Junichi TakeuchiFumio Nakano
    • H03K19094
    • H03K19/018528
    • An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL. An output buffer circuit of PECL according to the present invention comprises: a first output terminal; a second output terminal; a first resistor connected between the first output terminal and a output terminal of a common level generator; a second resister connected between the second output terminal and the output terminal of the common level generator; and a driver circuit which makes a current from the first output terminal to the second output terminal through the first resistor and second resistor when a first input signal and a second input signal complementary to the first input signal result a first data, and makes a current from the second output terminal to the first output terminal through the second resistor and the first resistor when the first input signal and the second input signal result a second data; a common level which follows its fluctuation to that of power source is supplied to the connecting point of the first and second resistors.
    • 伪发射极耦合逻辑(PECL)的输出缓冲电路使用由电阻分割产生的公共电平,使得公共电平不稳定以跟随电源变化的梯度和输出缓冲电路的输出信号电平 容易脱离PECL的水平。 根据本发明的PECL的输出缓冲电路包括:第一输出端; 第二输出端子; 连接在所述第一输出端子和公共电平发生器的输出端子之间的第一电阻器; 连接在第二输出端子和公共电平发生器的输出端子之间的第二电阻器; 以及驱动电路,当与所述第一输入信号互补的第一输入信号和第二输入信号产生第一数据时,通过所述第一电阻器和所述第二电阻器将从所述第一输出端子流到所述第二输出端子的电流产生电流 当第一输入信号和第二输入信号产生第二数据时,通过第二电阻器和第一电阻器从第二输出端子到第一输出端子; 将其波动与电源的波动的共同电平提供给第一和第二电阻器的连接点。