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    • 7. 发明授权
    • Capacitor for semiconductor integrated circuit
    • 半导体集成电路电容器
    • US5745336A
    • 1998-04-28
    • US417839
    • 1995-04-06
    • Katsuaki SaitoMichio OhueTakuya FukudaJaiHo ChoiYukinobu Miyamoto
    • Katsuaki SaitoMichio OhueTakuya FukudaJaiHo ChoiYukinobu Miyamoto
    • H01G7/06H01L21/02H01L27/115H01G4/06
    • H01L27/11502H01G7/06H01L28/55
    • A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed. As a result, a fact that an oxide of each electrode, which deteriorates the relative permittivity, is formed on the interface between the electrode and the ferroelectric material is prevented, and a large capacity can be realized with respect to the area of the substrate because the ferroelectric thin film is formed into the columnar and elongated shape, resulting in that the capacitance of the capacitor is not reduced in which the electrodes and the oxide dielectric material having a high permittivity are, in series, connected to each other. The capacitor is formed into a DRAM or an FRAM memory cell so as to realize a semiconductor memory revealing a high degree of integration and a high processing speed.
    • 根据本发明的半导体集成电路装置具有电容器,其形成为在其基板上形成MOS晶体管之后形成铁电薄膜,由例如PbZrTiO 3或SrTiO 3制成的铁电薄膜 或类似物形成为柱状,以形成与所述柱状铁电薄膜的侧壁部分直接接触的电极,并且去除顶部部分。 结果,防止了在电极和铁电材料之间的界面上形成各种电极的氧化物,导致相对介电常数下降的事实,因此能够相对于基板的面积实现大容量,因为 铁电薄膜形成为柱状和细长形状,导致电容器的电容不降低,其中具有高介电常数的电极和氧化物介电材料串联连接。 电容器形成为DRAM或FRAM存储单元,以实现显示高集成度和高​​处理速度的半导体存储器。