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1. 发明授权

US5068804A Document input method and apparatus 失效
标题翻译：文件输入法和装置
公开(公告)号：US5068804A
公开(公告)日：1991-11-26
申请号：US520133
申请日：1990-05-07
申请人： Tan Watanabe , Hideki Nishino , Hidefumi Iwami , Kuniaki Tabata
发明人： Tan Watanabe , Hideki Nishino , Hidefumi Iwami , Kuniaki Tabata
IPC分类号： G06F17/21 , G06T11/20
CPC分类号： G06T11/206
摘要： An input method and an input apparatus wherein a sketch read by an image scanner is displayed on the display, the class of component figure is designated thereon, characteristic values are input, and positions of characteristic points are designated such that a figure of fair copy is automatically prepared. Further, the sketch and the figure of fair copy are displayed being superposed upon each other while modifying the brightness or color so that the results of input can be easily recognized, making it possible to reduce the work for inputting the figure and to easily determine the size and position of the figure on the document which is a constituent component. In preparing the figure of fair copy by recognizing through a pattern recognition device the sketch that is input by the image scanner, furthermore, those portions that were not properly recognized are input again by the above method and apparatus.
摘要翻译：一种输入方法和输入装置，其中在显示器上显示由图像扫描器读取的草图，在其上指定分量图形的类别，输入特征值，并且指定特征点的位置，使得公平拷贝的图形为自动准备此外，在修改亮度或颜色的同时，将草图和公平复制图叠加在一起，使得可以容易地识别输入的结果，从而可以减少输入图形的工作并且容易地确定在作为组成部分的文件上的数字的大小和位置。在通过图案识别装置识别由图像扫描仪输入的草图的情况下准备公平拷贝的图形，此外，通过上述方法和装置再次输入未被正确识别的那些部分。

2. 发明授权

US4308561A Miniature computer 失效
标题翻译：微型计算机
公开(公告)号：US4308561A
公开(公告)日：1981-12-29
申请号：US149582
申请日：1980-05-14
申请人： Toru Onodera , Akira Ohsawa , Hideki Nishino , Masao Watari
发明人： Toru Onodera , Akira Ohsawa , Hideki Nishino , Masao Watari
IPC分类号： G06F9/455 , G06F15/02 , G06F15/78 , H05K1/14 , G11B5/09 , G11B5/02
CPC分类号： G06F15/7864 , H05K1/14
摘要： A reproducing circuit is provided for reproducing digital information recorded in a cassette tape by frequency modulation in which different first and second digital logic levels are respectively represented by first and second repeated signals having respective first and second repeated frequencies, the first repeated frequency being higher than the second. A pulse forming circuit produces first and second pulse signals having the first and second repeated frequencies in response to the signals recorded on the cassette tape. The first or second pulse signals are applied to a one-shot circuit as a trigger signal and to the control input terminal of a flip-flop circuit as a control signal. The output of the one-shot circuit is supplied to the data input terminal of the flip-flop circuit, whereby reproduced digital information corresponding to the digital information recorded on the cassette tape is derived from the output terminal of the flip-flop circuit.
摘要翻译：再现电路用于通过频率调制再现记录在盒式磁带中的数字信息，其中不同的第一和第二数字逻辑电平分别由具有相应的第一和第二重复频率的第一和第二重复信号表示，第一重复频率高于第二。脉冲形成电路响应于记录在盒式磁带上的信号产生具有第一和第二重复频率的第一和第二脉冲信号。第一或第二脉冲信号作为触发信号施加到单触发电路，并作为控制信号施加到触发器电路的控制输入端。单触发电路的输出被提供给触发器电路的数据输入端，由此从触发器电路的输出端导出与记录在盒式磁带上的数字信息对应的再现的数字信息。

3. 发明申请

US20080128826A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION METHOD FOR THE SAME 审中-公开
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20080128826A1
公开(公告)日：2008-06-05
申请号：US11945605
申请日：2007-11-27
申请人： Shingo Fukamizu , Yutaka Nabeshima , Hideki Nishino
发明人： Shingo Fukamizu , Yutaka Nabeshima , Hideki Nishino
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L23/49562 , H01L23/4952 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05552 , H01L2224/05553 , H01L2224/05647 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099
摘要： The semiconductor integrated circuit includes: a power transistor formed on a semiconductor substrate; a plurality of first metal patterns and a plurality of second metal patterns formed right above the power transistor for acting as first and second electrodes of the power transistor; a first bus electrically connected with the first metal patterns; a second bus electrically connected with the second metal patterns; and one contact pad provided for each of the first and second buses. Each of the first and second buses has at least one slit.
摘要翻译：半导体集成电路包括：形成在半导体衬底上的功率晶体管; 形成在功率晶体管正上方的多个第一金属图形和多个第二金属图案，用作功率晶体管的第一和第二电极; 与所述第一金属图案电连接的第一总线; 与所述第二金属图案电连接的第二总线; 以及为第一和第二总线中的每一个设置的一个接触垫。第一和第二总线中的每一个具有至少一个狭缝。

4. 发明授权

US06979970B2 Sensorless motor driving device and its driving method 有权
标题翻译：无传感器电机驱动装置及其驱动方法
公开(公告)号：US06979970B2
公开(公告)日：2005-12-27
申请号：US10878442
申请日：2004-06-29
申请人： Taishi Iwanaga , Yasunori Yamamoto , Hideki Nishino
发明人： Taishi Iwanaga , Yasunori Yamamoto , Hideki Nishino
IPC分类号： H02P27/08 , H02P3/08 , H02P5/00 , H02P6/08 , H02P6/18 , H02P6/20 , H02P7/00
CPC分类号： H02P6/182
摘要： A PWM control section (1) gently changes phase currents (Iu, Iv, and Iw) under a current driving control over a pre-drive circuit (2) and an output circuit (3). The pre-drive circuit (2) suspends energizing of the specific motor coil (Mu, Mv, and Mw) according to a PWM disable signal (NPWM) at PWM disable periods. A self-commutation circuit (5) performs zero crossing detection according to a BEMF detection signal (DZC) during BEMF detection periods. A count section (7) selects either a self-commutation signal (SC) or a forced commutation signal (FC) as a commutation signal (CS), whichever enters earlier, and, based on its intervals, generates the PWM disable signal (NPWM) and the BEMF detection signal (DZC). The BEMF detection period starts after the start of the PWM disable period, and finishes together with the PWM disable period at the switching of the energization phases.
摘要翻译： PWM控制部分（1）在电流驱动控制下在预驱动电路（2）和输出电路（3）上轻轻地改变相电流（Iu，Iv和Iw）。在PWM禁止期间，预驱动电路（2）根据PWM禁止信号（NPWM）暂停特定电动机线圈的通电（Mu，Mv和Mw）。自整流电路（5）在BEMF检测期间根据BEMF检测信号（DZC）进行过零检测。计数部分（7）选择自换换信号（SC）或强制换向信号（FC）作为换向信号（CS），以较早者为准，并且基于其间隔产生PWM禁止信号（NPWM ）和BEMF检测信号（DZC）。 BEMF检测周期在PWM禁止周期开始后开始，并在通电阶段切换时与PWM禁止周期一起完成。

5. 发明授权

US06874744B2 Stand for supporting a display in multiple orientations and a display used in combination with said stand 有权
公开(公告)号：US06874744B2
公开(公告)日：2005-04-05
申请号：US10080518
申请日：2002-02-25
申请人： Scott Rawlings , Hideki Nishino , Konrad Pollmann , David Sayler
发明人： Scott Rawlings , Hideki Nishino , Konrad Pollmann , David Sayler
IPC分类号： G01S19/05 , F16M11/06 , F16M11/10 , E04G3/00 , A47F5/02
CPC分类号： F16M13/00 , F16M11/041 , F16M11/105 , F16M11/2021 , F16M2200/024 , F16M2200/044 , F16M2200/08 , Y10S248/919 , Y10S248/922
摘要： An adjustable stand for rotatably and releaseably supporting a flat panel display is disclosed together with a display device usable with the stand. The display includes a boss projecting from a rear surface thereof, which boss is received in an arc-shaped channel in a plate portion of the stand. The stand further includes two hingedly connected legs and selective locking devices for controlling the angle between the legs, thereby allowing the stand hold the display in a variety of orientations with respect to a horizontal support surface.

6. 发明授权

US4253143A Miniature computer capable of using a conventional audio cassette tape deck as an auxiliary memory 失效
标题翻译：能够使用传统音频盒式磁带录像机作为辅助存储器的微型计算机
公开(公告)号：US4253143A
公开(公告)日：1981-02-24
申请号：US898996
申请日：1978-04-21
申请人： Toru Onodera , Akira Ohsawa , Hideki Nishino , Masao Watari
发明人： Toru Onodera , Akira Ohsawa , Hideki Nishino , Masao Watari
IPC分类号： G06F9/455 , G06F15/02 , G06F15/78 , H05K1/14 , G06F3/023 , G06F3/147 , G06F9/22
CPC分类号： G06F15/7864 , H05K1/14
摘要： A minature computer comprising a main section which includes a central processor, a read only memory storing a monitor program, a random access memory for executing the monitor program and a controlling circuit for peripheral equipments developed which has a hand-held controller electrically connected to the main section through a flat cable, having a keyboard and display device such that the keyboard has keys of a numeral 0 to 9 and the alpha characters A to Z for enabling symbolic languages to be input according to an assembler program. The assembler program is stored in the read only memory and the symbolic languages are converted to corresponding machine languages. The main section has a first jack capable of inputting a program from a audio cassette tape deck and a second jack capable of storing a program in a audio cassette tape deck. The main section also has third and fourth jacks which control the operation of the audio cassette tape decks connected to the first two jacks.
摘要翻译：一种微型计算机，包括主部分，其包括中央处理器，存储监视程序的只读存储器，用于执行监视程序的随机存取存储器和用于开发的用于外围设备的控制电路，其具有电连接到主要部分通过扁平电缆，具有键盘和显示装置，使得键盘具有数字0至9的键和用于使符号语言根据汇编程序输入的字母A至Z。汇编程序存储在只读存储器中，符号语言被转换为相应的机器语言。主要部分具有能够从音频盒式磁带卡座输入程序的第一插孔和能够将程序存储在音频盒式磁带卡座中的第二插孔。主要部分还具有第三和第四插孔，其控制连接到前两个插孔的音频盒式磁带机的操作。

7. 发明申请

US20080035808A1 Stand for supporting a display in multiple orientations and a display used in combination with said stand 审中-公开
标题翻译：用于支持多个方向的显示器和与所述支架组合使用的显示器
公开(公告)号：US20080035808A1
公开(公告)日：2008-02-14
申请号：US11812365
申请日：2007-06-18
申请人： Scott Rawlings , Hideki Nishino , Konrad Pollmann , David Sayler
发明人： Scott Rawlings , Hideki Nishino , Konrad Pollmann , David Sayler
IPC分类号： F16M11/00
CPC分类号： F16M13/00 , F16M11/041 , F16M11/105 , F16M11/2021 , F16M2200/024 , F16M2200/044 , F16M2200/08 , Y10S248/919 , Y10S248/922
摘要： An adjustable stand for rotatably and releaseably supporting a flat panel display is disclosed together with a display device usable with the stand. The display includes a boss projecting from a rear surface thereof, which boss is received in an arc-shaped channel in a plate portion of the stand. The stand further includes two hingedly connected legs and selective locking devices for controlling the angle between the legs, thereby allowing the stand hold the display in a variety of orientations with respect to a horizontal support surface.
摘要翻译：公开了一种用于可转动和可释放地支撑平板显示器的可调节支架，以及可与展台一起使用的显示装置。显示器包括从其后表面突出的凸台，该凸台被接收在支架的板部分中的弧形通道中。支架还包括两个铰接连接的腿和用于控制腿部之间的角度的选择性锁定装置，从而允许支架以相对于水平支撑表面的各种取向保持显示器。

8. 发明申请

US20060214529A1 Three-phase DC brushless motor and winding method 有权
公开(公告)号：US20060214529A1
公开(公告)日：2006-09-28
申请号：US11385334
申请日：2006-03-21
申请人： Hideki Nishino , Kiyotaka Tanimoto , Taishi Iwanaga , Shinichi Kuroshima , Yoshiaki Igarashi
发明人： Hideki Nishino , Kiyotaka Tanimoto , Taishi Iwanaga , Shinichi Kuroshima , Yoshiaki Igarashi
IPC分类号： H02K3/00 , G05B11/28
CPC分类号： H02K3/28
摘要： A three-phase DC brushless motor and coil winding method provide a coil winding enabling consistent starting with PWM sensorless driving by suppressing the DC offset component of the induced voltage resulting from an imbalance in the motor coil windings. The method of winding the armature winding of the three-phase DC brushless motor renders the difference in mutual inductance substantially zero.

9. 发明授权

US07088067B2 Motor driving apparatus and motor driving method 有权
公开(公告)号：US07088067B2
公开(公告)日：2006-08-08
申请号：US11191853
申请日：2005-07-27
申请人： Yasunori Yamamoto , Hideaki Mori , Shinichi Kuroshima , Hideki Nishino , Taishi Iwanaga
发明人： Yasunori Yamamoto , Hideaki Mori , Shinichi Kuroshima , Hideki Nishino , Taishi Iwanaga
IPC分类号： H02P7/00
CPC分类号： H02P6/10 , H02P6/18 , H02P2209/07
摘要： A motor driving apparatus has a driver circuit configuration capable of individually adjusting three phase coil currents. Coil current waveforms are formed to have a total of three phase shaft direction forces to be zero in compliance with predetermined mathematical expressions, and thus, three phase coil current profiles can be made independent of one another, and vibration-causing factors attributed to the fact that a certain phase is in an non-energized state are corrected by adjusting the current profiles of the other phases. Consequently, the vibration and the noise can be reduced.

10. 发明授权

US06424106B1 Motor 有权
公开(公告)号：US06424106B1
公开(公告)日：2002-07-23
申请号：US09820450
申请日：2001-03-29
申请人： Makoto Gotou , Masaaki Ochi , Hideaki Mori , Hideki Nishino
发明人： Makoto Gotou , Masaaki Ochi , Hideaki Mori , Hideki Nishino
IPC分类号： H02P602
摘要： FET power transistors of a power supplying part execute high-frequency switching operation and form current paths to three-phase windings. A voltage detecting part compares terminal voltages of the three-phase windings and produces a detected pulse signal in response to a comparison result. A state shifting part and an activation control part control active periods of the FET power transistors in response to the detected pulse signal. A commanding part produces a command signal in response to an output pulse signal of the voltage detecting means. A switching operation block produces a switching pulse signal in response to a comparison result of a current-detection signal with the command signal, and causes at least an FET power transistor of the power supplying part to perform high-frequency switching in response to the switching pulse signal. The state shifting part produces a timing signal after an adjust time from the detection of the detected pulse signal and shift-holds a holding state in response to the timing signal. The state shifting part changes the adjust time smaller in case that the command signal is larger than a predetermined value, thereby making the product value of the adjust time and the rotational speed smaller in the case.

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