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    • 6. 发明授权
    • Sensorless motor driving device and its driving method
    • 无传感器电机驱动装置及其驱动方法
    • US06979970B2
    • 2005-12-27
    • US10878442
    • 2004-06-29
    • Taishi IwanagaYasunori YamamotoHideki Nishino
    • Taishi IwanagaYasunori YamamotoHideki Nishino
    • H02P27/08H02P3/08H02P5/00H02P6/08H02P6/18H02P6/20H02P7/00
    • H02P6/182
    • A PWM control section (1) gently changes phase currents (Iu, Iv, and Iw) under a current driving control over a pre-drive circuit (2) and an output circuit (3). The pre-drive circuit (2) suspends energizing of the specific motor coil (Mu, Mv, and Mw) according to a PWM disable signal (NPWM) at PWM disable periods. A self-commutation circuit (5) performs zero crossing detection according to a BEMF detection signal (DZC) during BEMF detection periods. A count section (7) selects either a self-commutation signal (SC) or a forced commutation signal (FC) as a commutation signal (CS), whichever enters earlier, and, based on its intervals, generates the PWM disable signal (NPWM) and the BEMF detection signal (DZC). The BEMF detection period starts after the start of the PWM disable period, and finishes together with the PWM disable period at the switching of the energization phases.
    • PWM控制部分(1)在电流驱动控制下在预驱动电路(2)和输出电路(3)上轻轻地改变相电流(Iu,Iv和Iw)。 在PWM禁止期间,预驱动电路(2)根据PWM禁止信号(NPWM)暂停特定电动机线圈的通电(Mu,Mv和Mw)。 自整流电路(5)在BEMF检测期间根据BEMF检测信号(DZC)进行过零检测。 计数部分(7)选择自换换信号(SC)或强制换向信号(FC)作为换向信号(CS),以较早者为准,并且基于其间隔产生PWM禁止信号(NPWM )和BEMF检测信号(DZC)。 BEMF检测周期在PWM禁止周期开始后开始,并在通电阶段切换时与PWM禁止周期一起完成。
    • 8. 发明授权
    • Miniature computer
    • 微型计算机
    • US4308561A
    • 1981-12-29
    • US149582
    • 1980-05-14
    • Toru OnoderaAkira OhsawaHideki NishinoMasao Watari
    • Toru OnoderaAkira OhsawaHideki NishinoMasao Watari
    • G06F9/455G06F15/02G06F15/78H05K1/14G11B5/09G11B5/02
    • G06F15/7864H05K1/14
    • A reproducing circuit is provided for reproducing digital information recorded in a cassette tape by frequency modulation in which different first and second digital logic levels are respectively represented by first and second repeated signals having respective first and second repeated frequencies, the first repeated frequency being higher than the second. A pulse forming circuit produces first and second pulse signals having the first and second repeated frequencies in response to the signals recorded on the cassette tape. The first or second pulse signals are applied to a one-shot circuit as a trigger signal and to the control input terminal of a flip-flop circuit as a control signal. The output of the one-shot circuit is supplied to the data input terminal of the flip-flop circuit, whereby reproduced digital information corresponding to the digital information recorded on the cassette tape is derived from the output terminal of the flip-flop circuit.
    • 再现电路用于通过频率调制再现记录在盒式磁带中的数字信息,其中不同的第一和第二数字逻辑电平分别由具有相应的第一和第二重复频率的第一和第二重复信号表示,第一重复频率高于 第二。 脉冲形成电路响应于记录在盒式磁带上的信号产生具有第一和第二重复频率的第一和第二脉冲信号。 第一或第二脉冲信号作为触发信号施加到单触发电路,并作为控制信号施加到触发器电路的控制输入端。 单触发电路的输出被提供给触发器电路的数据输入端,由此从触发器电路的输出端导出与记录在盒式磁带上的数字信息对应的再现的数字信息。