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1. 发明申请

US20050037524A1 Method of manufacturing semiconductor device having trench isolation 失效
公开(公告)号：US20050037524A1
公开(公告)日：2005-02-17
申请号：US10949451
申请日：2004-09-27
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L21/66 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

2. 发明授权

US07144764B2 Method of manufacturing semiconductor device having trench isolation 失效
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US07144764B2
公开(公告)日：2006-12-05
申请号：US10949451
申请日：2004-09-27
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L21/762
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
摘要翻译：本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3）。为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。

3. 发明申请

US20060249756A1 Method of manufacturing semiconductor device having trench isolation 审中-公开
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US20060249756A1
公开(公告)日：2006-11-09
申请号：US11481799
申请日：2006-07-07
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L29/768
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.
摘要翻译：半导体器件包括多个不同功能的电路部分，每个电路部分通过在通过顺序地堆叠半导体衬底，埋入绝缘膜和半导体层而获得的SOI衬底上包括MOS晶体管构成。该半导体器件包括第一和第二部分。第一电路部分通过被设置在半导体层的上部上的第一绝缘膜和穿过半导体层的第二绝缘膜包围而被隔离，以到达掩埋绝缘膜。

4. 发明授权

US06841400B2 Method of manufacturing semiconductor device having trench isolation 失效
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US06841400B2
公开(公告)日：2005-01-11
申请号：US10216363
申请日：2002-08-12
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L21/66 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
摘要翻译：本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。在图案化氮化膜（22）之后，测量SOI层3的厚度（S2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S3）。为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。使用所确定的蚀刻条件，并且通过使用图案化氮化物膜22作为蚀刻掩模形成沟槽TR2（S4）。

5. 发明申请

US20070176235A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070176235A1
公开(公告)日：2007-08-02
申请号：US11627167
申请日：2007-01-25
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.
摘要翻译：在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此，源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。此外，源极/漏极区域形成为穿透硅层。

6. 发明申请

US20060180861A1 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20060180861A1
公开(公告)日：2006-08-17
申请号：US11341444
申请日：2006-01-30
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/78615
摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.
摘要翻译：在半导体器件中，在由SOI衬底构成的SOI衬底的顶部上设置栅电极，杂质扩散区域，体电位固定区域，第一绝缘体和虚设栅电极，所述SOI衬底由下面的硅衬底，埋入绝缘体和半导体层。杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

7. 发明授权

US08350331B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08350331B2
公开(公告)日：2013-01-08
申请号：US11627167
申请日：2007-01-25
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/84
摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.
摘要翻译：在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此，源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。此外，源极/漏极区域形成为穿透硅层。

8. 发明授权

US07511342B2 Semiconductor device having SOI structure and method for manufacturing the same 有权
标题翻译：具有SOI结构的半导体器件及其制造方法
公开(公告)号：US07511342B2
公开(公告)日：2009-03-31
申请号：US11341444
申请日：2006-01-30
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigeto Maegawa
IPC分类号： H01L31/0392
CPC分类号： H01L29/66772 , H01L29/78615
摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.
摘要翻译：在半导体器件中，在由SOI衬底，底层硅衬底，埋入绝缘体和半导体层。杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

9. 发明申请

US20080179676A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20080179676A1
公开(公告)日：2008-07-31
申请号：US11971434
申请日：2008-01-09
申请人： Yuichi HIRANO , Takashi Ipposhi , Toshiaki Iwamatsu , Yukio Maki , Mikio Tsujiuchi
发明人： Yuichi HIRANO , Takashi Ipposhi , Toshiaki Iwamatsu , Yukio Maki , Mikio Tsujiuchi
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1203
摘要： While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.
摘要翻译：在减小SRAM单元的形成面积的同时，抑制了各个晶体管的电特性的变化。在SOI板中形成的SRAM单元中，驱动晶体管（其也是存取晶体管的源极/漏极区域）的漏极区域与负载晶体管的漏极区域之间的电耦合以及电耦合另一个驱动晶体管的漏极区（也是另一个存取晶体管的源极/漏极区）和另一个负载晶体管的漏极区通过在隔离氧化膜下使用SOI层而形成的布线结构来建立，该SOI层是部分沟槽隔离，分别。

10. 发明申请

US20060289904A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20060289904A1
公开(公告)日：2006-12-28
申请号：US11425072
申请日：2006-06-19
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L29/76
CPC分类号： H01L29/458 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

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