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1. 发明授权

US5991197A Semiconductor memory device having data protection feature 失效
标题翻译：具有数据保护功能的半导体存储器件
公开(公告)号：US5991197A
公开(公告)日：1999-11-23
申请号：US46583
申请日：1998-03-24
申请人： Taku Ogura , Atsushi Ohba , Tsuyoshi Honma , Kazuo Kobayashi
发明人： Taku Ogura , Atsushi Ohba , Tsuyoshi Honma , Kazuo Kobayashi
IPC分类号： G11C16/02 , G11C16/22 , G11C16/04
CPC分类号： G11C16/22
摘要： A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.
摘要翻译：复位停电模式指定信号和第一和第二写保护信号被提供给控制电路。根据这些外部控制信号的状态，为存储器阵列的每个存储块组设置无条件禁止，无条件许可和数据重写保护状态的锁定位（LB）依赖性的状态。因此，写保护状态可以灵活地设置为非易失性半导体存储器件。

2. 发明授权

US08809247B2 Cleaning composition and method for cleaning substrate for electronic device 有权
标题翻译：用于清洁电子设备基板的清洁组合物和方法
公开(公告)号：US08809247B2
公开(公告)日：2014-08-19
申请号：US12867468
申请日：2009-02-13
申请人： Makoto Hidaka , Taku Ogura
发明人： Makoto Hidaka , Taku Ogura
IPC分类号： C11D3/04 , H01L21/02 , C11D3/39 , C11D7/10 , C11D7/26 , C11D11/00 , H01L29/16
CPC分类号： H01L21/02052 , C11D3/3947 , C11D7/10 , C11D7/265 , C11D11/0047 , H01L29/1608
摘要： A cleaning composition which is capable of removing both organic soiling and particulate soiling adhered to a substrate for an electronic device with a high degree of cleanliness, and which also has minimal impact on the environment, as well as a method of cleaning a substrate for an electronic device. The present invention relates to a cleaning composition used for cleaning a substrate for an electronic device including a water-soluble salt (A) containing a transition metal, a chelating agent (B) and a peroxide (C), wherein the amount of the chelating agent (B) is not less than 0.5 molar equivalents relative to the amount of the water-soluble salt (A) containing a transition metal.
摘要翻译：一种清洁组合物，其能够除去附着在具有高清洁度的电子设备的基板上并且对环境影响最小的有机污染物和微粒污染物，以及清洁基板的方法，电子设备。本发明涉及一种清洗组合物，其用于清洗包含含有过渡金属的水溶性盐（A），螯合剂（B）和过氧化物（C））的电子器件用基材，其中螯合剂试剂（B）相对于含有过渡金属的水溶性盐（A）的量不小于0.5摩尔当量。

3. 发明授权

US08339862B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08339862B2
公开(公告)日：2012-12-25
申请号：US12343552
申请日：2008-12-24
申请人： Natsuo Aiika , Shoii Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Aiika , Shoii Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： G11C16/06 , G11C11/34 , H01L29/792
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11524
摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.
摘要翻译：根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。

4. 发明申请

US20120080053A1 METHOD FOR CLEANING OF SEMICONDUCTOR SUBSTRATE AND ACIDIC SOLUTION 审中-公开
标题翻译：清洗半导体衬底和酸性溶液的方法
公开(公告)号：US20120080053A1
公开(公告)日：2012-04-05
申请号：US13266255
申请日：2010-04-30
申请人： Makoto Hidaka , Taku Ogura , Maiko Kikuchi , Motohiro Kageyama , Masayuki Takashima
发明人： Makoto Hidaka , Taku Ogura , Maiko Kikuchi , Motohiro Kageyama , Masayuki Takashima
IPC分类号： B08B3/08 , C11D7/60 , C23G1/02
CPC分类号： C11D3/046 , C11D3/2075 , C11D3/33 , C11D3/3947 , C11D7/10 , C11D7/265 , C11D7/3245 , C11D11/0047 , H01L21/02052
摘要： Disclosed is a cleaning method which can remove, particularly, all of an organic contaminant, a particle contaminant, and a metal contaminant adhered to a semiconductor substrate at a high cleaning level, and which can realize the reduction in environmental load caused by the cleaning. The method of cleaning the semiconductor substrate includes a first cleaning process of cleaning the semiconductor substrate with a cleaning composition including a transition-metal-containing water-soluble salt (A), a chelating agent (B1), and a peroxide (C), a ratio of the chelating agent (B1) to the transition-metal-containing water-soluble salt (A) being 0.5 molar equivalent or more; and a second cleaning process of cleaning the semiconductor substrate, which is cleaned through the first cleaning process, with an acidic solution containing a chelating agent (B2).
摘要翻译：公开了一种可以清除特别是全部有机污染物，颗粒污染物和在高清洁水平附着于半导体衬底上的金属污染物的清洁方法，并且能够实现由清洁引起的环境负荷的降低。清洗半导体衬底的方法包括用包含含过渡金属的水溶性盐（A），螯合剂（B1）和过氧化物（C）的清洁组合物清洗半导体衬底的第一清洁工艺，螯合剂（B1）与过渡金属的水溶性盐（A）的比例为0.5摩尔当量以上; 以及通过第一清洗处理清洗半导体衬底的第二清洁工艺，其中含有螯合剂（B2）的酸性溶液。

5. 发明授权

US08106443B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08106443B2
公开(公告)日：2012-01-31
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

6. 发明授权

US07542363B2 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US07542363B2
公开(公告)日：2009-06-02
申请号：US11082926
申请日：2005-03-18
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

7. 发明申请

US20070297251A1 Semiconductor memory device having memory block configuration 失效
公开(公告)号：US20070297251A1
公开(公告)日：2007-12-27
申请号：US11819203
申请日：2007-06-26
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

8. 发明申请

US20070285146A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070285146A1
公开(公告)日：2007-12-13
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

9. 发明授权

US07307886B2 Nonvolatile memory device including circuit formed of thin film transistors 有权
标题翻译：包括由薄膜晶体管形成的电路的非易失性存储器件
公开(公告)号：US07307886B2
公开(公告)日：2007-12-11
申请号：US11482019
申请日：2006-07-07
申请人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
发明人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
IPC分类号： G11C11/34 , G11C8/00
CPC分类号： G11C16/344 , G11C7/06 , G11C16/0416 , G11C16/12 , G11C16/345 , G11C16/3477 , G11C2207/005
摘要： A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.
摘要翻译：晶体管被布置为将由薄膜晶体管形成的读出放大器与电耦合到读出放大器的数据线电隔离。当写驱动器驱动数据线时，施加控制信号以将数据线与读出放大器隔离。

10. 发明授权

US07230852B2 Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time 有权
标题翻译：非易失性半导体存储器件允许在短时间内进行有效的编程操作和擦除操作
公开(公告)号：US07230852B2
公开(公告)日：2007-06-12
申请号：US10940812
申请日：2004-09-15
申请人： Hidenori Mitani , Fumihiko Nitta , Tadaaki Yamauchi , Taku Ogura
发明人： Hidenori Mitani , Fumihiko Nitta , Tadaaki Yamauchi , Taku Ogura
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C29/84 , G11C16/10 , G11C16/16 , G11C16/22 , G11C16/30 , G11C16/344
摘要： Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.
摘要翻译：直到脉冲施加次数n达到12为止，作为前半脉冲，脉冲被设置为具有固定为2ms的宽度，并且其电压每次都增加。作为后半脉冲，脉冲被设置为具有固定为3ms的宽度，并且每次都增加脉冲电压直到达到最大电压。达到最大电压后，首先施加3 ms宽度的脉冲两次，施加最大电压的4 ms宽度的脉冲两次，最大电压为5 ms的脉冲宽度被应用两次。即使在达到最大电压之后，阈值电压的时间变化也可以更线性化。因此，可以提供允许在短时间段内进行有效的编程操作和擦除操作的非易失性半导体存储器件。

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