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1. 发明授权

US08208303B2 Semiconductor memory device having memory block configuration 失效
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US08208303B2
公开(公告)日：2012-06-26
申请号：US13178182
申请日：2011-07-07
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C11/34 , G11C7/00 , G11C8/00
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory apparatus includes a control circuit, a plurality of memory arrays, each of which contains a plurality of memory cells, and a current detecting circuit. The current detecting circuit measures a quantity of a current of a first memory array. A redundancy information is changed when the quantity of the current of the first memory array is over a first current quantity detected by the current detecting circuit. The control circuit controls an access to the memory arrays, and changes the access to the first memory array to a second memory array in accordance with the redundancy information.
摘要翻译：存储装置包括控制电路，多个存储器阵列，每个存储器阵列都包含多个存储单元，以及电流检测电路。电流检测电路测量第一存储器阵列的电流量。当第一存储器阵列的电流量超过由电流检测电路检测到的第一电流量时，冗余信息被改变。控制电路控制对存储器阵列的访问，并且根据冗余信息将对第一存储器阵列的访问改变为第二存储器阵列。

2. 发明授权

US08000159B2 Semiconductor memory device having memory block configuration 有权
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US08000159B2
公开(公告)日：2011-08-16
申请号：US12849254
申请日：2010-08-03
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C7/00 , G11C11/34 , G11C8/00
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.
摘要翻译：包括存储器垫的存储器阵列在二维状态下被布置成U形，并且在由存储器阵列未占据的区域中布置逻辑电路和模拟电路。这有助于在包括模拟和逻辑电路的外围电路和包括电源和数据焊盘的焊盘带之间的电源电压和信号的传输。模拟电路位于靠近电源焊盘的位置，因此受限于电源互连电阻引起的电压降。还可以在电源板附近分离电荷泵浦电源互连和外围电路电源互连。

3. 发明授权

US07782672B2 Semiconductor memory device having memory block configuration 有权
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US07782672B2
公开(公告)日：2010-08-24
申请号：US12251894
申请日：2008-10-15
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C11/34 , G11C7/00 , G11C8/00
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.
摘要翻译：包括存储器垫的存储器阵列在二维状态下被布置成U形，并且在由存储器阵列未占据的区域中布置逻辑电路和模拟电路。这有助于在包括模拟和逻辑电路的外围电路和包括电源和数据焊盘的焊盘带之间的电源电压和信号的传输。模拟电路位于靠近电源焊盘的位置，因此受限于电源互连电阻引起的电压降。还可以在电源板附近分离电荷泵浦电源互连和外围电路电源互连。

4. 发明授权

US07742334B2 Nonvolatile semiconductor memory device for writing multivalued data 有权
标题翻译：用于写入多值数据的非易失性半导体存储器件
公开(公告)号：US07742334B2
公开(公告)日：2010-06-22
申请号：US11819016
申请日：2007-06-25
申请人： Tomoyuki Fujisawa , Hikaru Shibahara , Hidenori Mitani , Akihiko Kanda
发明人： Tomoyuki Fujisawa , Hikaru Shibahara , Hidenori Mitani , Akihiko Kanda
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.
摘要翻译：存储器阵列的存储单元存储两个位。存储器阵列读出放大器在验证操作中提供两个位。页面缓冲器中的两位存储对应存储单元的写入目标值。掩码缓冲器中的每个位存储要在对应的存储器单元上进行的定义处理的值。当对应于所选存储单元的掩码缓冲器中的位为“0”时，写入驱动器施加写入脉冲。验证电路将存储器阵列读出放大器提供的两位与页缓冲器中相应的两位进行比较，当比较结果表示匹配时，将掩码缓冲器中的相应位从“0”更改为“1”。

5. 发明授权

US07652935B2 Semiconductor memory device capable of achieving narrower distribution width of threshold voltages of memory cells and method of data write in the same 有权
标题翻译：半导体存储器件能够实现较小的存储单元阈值电压分布宽度和数据写入方法
公开(公告)号：US07652935B2
公开(公告)日：2010-01-26
申请号：US12076787
申请日：2008-03-24
申请人： Tomoya Ogawa , Takashi Ito , Hidenori Mitani , Takashi Kono
发明人： Tomoya Ogawa , Takashi Ito , Hidenori Mitani , Takashi Kono
IPC分类号： G11C7/22
CPC分类号： G11C16/3404
摘要： When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.
摘要翻译：当数据写入序列开始时，最初写入数据被锁存在对应于一个存储器垫的数据锁存电路中。然后，将程序脉冲施加到存储器垫，并且执行从作为存储器垫中的数据写入目标位的存储单元读取的数据。此后，验证是否执行存储垫的确定。在存储器垫的验证操作完成之后，将程序脉冲施加到另一个存储器垫，并且执行另一存储器垫的验证操作。

6. 发明授权

US07164601B2 Multi-level nonvolatile semiconductor memory device utilizing a nonvolatile semiconductor memory device for storing binary data 有权
标题翻译：利用非易失性半导体存储器件存储二进制数据的多级非易失性半导体存储器件
公开(公告)号：US07164601B2
公开(公告)日：2007-01-16
申请号：US10936615
申请日：2004-09-09
申请人： Hidenori Mitani , Tadaaki Yamauchi , Taku Ogura
发明人： Hidenori Mitani , Tadaaki Yamauchi , Taku Ogura
IPC分类号： G11C16/00 , G11C16/08
CPC分类号： G11C8/10 , G11C7/1006 , G11C11/56 , G11C2211/5641
摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.
摘要翻译：通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。高字数据LW和下字数据UW被分别压缩成8位的字节数据，并存储在存储单元阵列中。

7. 发明申请

US20120002498A1 NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM 有权
标题翻译：非易失性存储器，数据处理设备和微处理器应用系统
公开(公告)号：US20120002498A1
公开(公告)日：2012-01-05
申请号：US13171849
申请日：2011-06-29
申请人： Toru Matsushita , Ken Matsubara , Takashi Iwase , Hidenori Mitani , Jun Setogawa , Fumiko Yamada
发明人： Toru Matsushita , Ken Matsubara , Takashi Iwase , Hidenori Mitani , Jun Setogawa , Fumiko Yamada
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.
摘要翻译：实现了与电源电压电平相对应地设置的多个电源电压模式中的非易失性存储器的操作稳定性。非易失性存储器配置有存储器阵列，电荷泵，用于选择电荷泵的输出电压的分配器，以及用于控制电荷泵和分配器的操作的定序器。非易失性存储器还设置有分析器，其向定序器通知在与电源电压电平相对应地设置的多个电源电压模式中选择性地指定的电源电压模式，并且检测通知给定序器和实际提供的电源电压，并且基于检测结果限制使用定序器的电荷泵和分配器的操作。因此，实现了非易失性存储器的操作稳定性。

8. 发明申请

US20110002170A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION 有权
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US20110002170A1
公开(公告)日：2011-01-06
申请号：US12849254
申请日：2010-08-03
申请人： Taku OGURA , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku OGURA , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C16/06
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.
摘要翻译：包括存储器垫的存储器阵列在二维状态下被布置成U形，并且在由存储器阵列未占据的区域中布置逻辑电路和模拟电路。这有助于在包括模拟和逻辑电路的外围电路和包括电源和数据焊盘的焊盘波段之间的电源电压和信号的传输。模拟电路位于靠近电源焊盘的位置，因此受限于电源互连电阻引起的电压降。还可以在电源板附近分离电荷泵浦电源互连和外围电路电源互连。

9. 发明授权

US07518929B2 Nonvolatile semiconductor memory device for writing multivalued data 有权
标题翻译：用于写入多值数据的非易失性半导体存储器件
公开(公告)号：US07518929B2
公开(公告)日：2009-04-14
申请号：US11819015
申请日：2007-06-25
申请人： Tomoyuki Fujisawa , Hikaru Shibahara , Hidenori Mitani , Akihiko Kanda
发明人： Tomoyuki Fujisawa , Hikaru Shibahara , Hidenori Mitani , Akihiko Kanda
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.
摘要翻译：存储器阵列的存储单元存储两个位。存储器阵列读出放大器在验证操作中提供两个位。页面缓冲器中的两位存储对应存储单元的写入目标值。掩码缓冲器中的每个位存储要在对应的存储器单元上进行的定义处理的值。当对应于所选存储单元的掩码缓冲器中的位为“0”时，写入驱动器施加写入脉冲。验证电路将存储器阵列读出放大器提供的两位与页缓冲器中相应的两位进行比较，当比较结果表示匹配时，将掩码缓冲器中的相应位从“0”更改为“1”。

10. 发明申请

US20090080252A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090080252A1
公开(公告)日：2009-03-26
申请号：US12326470
申请日：2008-12-02
申请人： Hidenori MITANI , Tadaaki YAMAUCHI , Taku OGURA
发明人： Hidenori MITANI , Tadaaki YAMAUCHI , Taku OGURA
IPC分类号： G11C7/08 , G11C16/26
CPC分类号： G11C8/10 , G11C7/1006 , G11C11/56 , G11C2211/5641
摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.
摘要翻译：通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。高字数据LW和下字数据UW被分别压缩成8位的字节数据，并存储在存储单元阵列中。

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