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1. 发明申请

US20090236722A1 SEMICONDUCTOR MEMORY CARD AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储卡和半导体存储器件
公开(公告)号：US20090236722A1
公开(公告)日：2009-09-24
申请号：US12400390
申请日：2009-03-09
申请人： Taku Nishiyama , Tetsuya Yamamoto , Naohisa Okumura , Takuya Futatsuyama
发明人： Taku Nishiyama , Tetsuya Yamamoto , Naohisa Okumura , Takuya Futatsuyama
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L23/5388 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.
摘要翻译：半导体存储卡包括具有外部形状的布线板，其中切口部分设置在第一长边缘处。布线板的第二表面包括沿着除了第一长边缘的切口部分之外的部分设置的连接焊盘。存储器件安装在布线板的第二表面上。存储装置包括沿着布线板的第一长边缘附近的长边定位布置的电极焊盘，并且一边设置成与连接焊盘的布置位置相对应。控制器装置堆叠在存储器件上。

2. 发明授权

US08274141B2 Semiconductor memory card and semiconductor memory device 有权
标题翻译：半导体存储卡和半导体存储器件
公开(公告)号：US08274141B2
公开(公告)日：2012-09-25
申请号：US12400390
申请日：2009-03-09
申请人： Taku Nishiyama , Tetsuya Yamamoto , Naohisa Okumura , Takuya Futatsuyama
发明人： Taku Nishiyama , Tetsuya Yamamoto , Naohisa Okumura , Takuya Futatsuyama
IPC分类号： H01L23/02
CPC分类号： H01L23/5388 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.
摘要翻译：半导体存储卡包括具有外部形状的布线板，其中切口部分设置在第一长边缘处。布线板的第二表面包括沿着除了第一长边缘的切口部分之外的部分设置的连接焊盘。存储器件安装在布线板的第二表面上。存储装置包括沿着布线板的第一长边缘附近的长边定位布置的电极焊盘，并且一边设置成与连接焊盘的布置位置相对应。控制器装置堆叠在存储器件上。

3. 发明授权

US08605503B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08605503B2
公开(公告)日：2013-12-10
申请号：US13711894
申请日：2012-12-12
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

4. 发明授权

US08565020B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08565020B2
公开(公告)日：2013-10-22
申请号：US13053796
申请日：2011-03-22
申请人： Takuya Futatsuyama , Toshifumi Hashimoto
发明人： Takuya Futatsuyama , Toshifumi Hashimoto
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436
摘要： A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.
摘要翻译：存储器包括字线，位线，各自具有连接到字线之一的栅极的存储单元，配置为驱动字线的电压的字线驱动器，以及经配置以经由该行线检测存储器单元的数据的读出放大器位线。存储单元串联在位线和源之间以构成单元串。在写入阶段的某个写入循环中，在验证操作时，字线驱动器增加连接到单元串中未选择的存储单元的任何未选择字线的验证电压。写入阶段包括多个写入循环。写入循环分别包括写入操作以在单元串中的选定的存储单元中写入数据，以及验证操作以验证数据被写入所选存储单元。

5. 发明授权

US08203885B2 Nonvolatile semiconductor memory system 有权
标题翻译：非易失性半导体存储器系统
公开(公告)号：US08203885B2
公开(公告)日：2012-06-19
申请号：US13178718
申请日：2011-07-08
申请人： Naofumi Abiko , Takuya Futatsuyama
发明人： Naofumi Abiko , Takuya Futatsuyama
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621 , G11C2211/5634 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.
摘要翻译：根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。

6. 发明申请

US20110216593A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20110216593A1
公开(公告)日：2011-09-08
申请号：US13108641
申请日：2011-05-16
申请人： KIYOFUMI SAKURAI , Takuya Futatsuyama
发明人： KIYOFUMI SAKURAI , Takuya Futatsuyama
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
摘要翻译：一种利用存储块控制闪速存储器编程的方法。该方法包括检查存储器块中的所选块是否属于第一组或第二组。该方法还包括当所选择的块属于第一组时从最小位地址执行编程。该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。

7. 发明授权

US07889537B2 Non-volatile memory device and method for writing data thereto 有权
标题翻译：用于向其写入数据的非易失性存储器件和方法
公开(公告)号：US07889537B2
公开(公告)日：2011-02-15
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

8. 发明授权

US07768844B2 Nonvolatile semiconductor memory device and method of driving the same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US07768844B2
公开(公告)日：2010-08-03
申请号：US12202601
申请日：2008-09-02
申请人： Satoru Takase , Takuya Futatsuyama
发明人： Satoru Takase , Takuya Futatsuyama
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418
摘要： This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions.
摘要翻译：本公开涉及包括存储单元阵列的存储器，该存储器单元阵列包括沿第一方向延伸的字线，沿与第一方向交叉的第二方向延伸的位线，以及提供分别对应于由该字形成的格子形式的交点的存储单元线和位线; 提供的读出放大器分别对应于位线和读取存储在存储器单元中的数据; 和位线驱动器，当数据被写入存储单元时，位线驱动器被提供给位线并操作位线，其中位线驱动器相对于格子的形式访问与第一存储器单元相对的第一存储器单元，在数据写入操作期间向相邻存储器单元提供数据，而不改变存储在与第一和第二方向上的第一存储单元相邻的存储单元中的数据。

9. 发明授权

US07729178B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07729178B2
公开(公告)日：2010-06-01
申请号：US11849891
申请日：2007-09-04
申请人： Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
发明人： Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/102
摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.
摘要翻译：非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持电路工作。然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。同时，将数据输出到奇数位线，并且确定奇数位线的电位。然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

10. 发明申请

US20080081467A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080081467A1
公开(公告)日：2008-04-03
申请号：US11842615
申请日：2007-08-21
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L27/105
摘要： A first insulating film, a second insulating film, a first resist pattern is formed on a semiconductor substrate, the second insulating film is etched to form a second-insulating-film pattern, a third insulating film is deposited over the second-insulating-film pattern to form a third-insulating-film pattern, the first insulating film is etched to form a first-insulating-film pattern, a fourth insulating film and a second resist pattern is formed over the first-insulating-film pattern, fourth insulating film is etched to form a fourth-insulating-film pattern, a fifth insulating film is deposited over the fourth-insulating-film pattern to form a fifth-insulating-film pattern, line parts of first-insulating-film pattern is etched to form a first-insulating-film pattern for wiring, a wiring film is formed over the first-insulating-film pattern for wiring, the wiring film is removed until the first-insulating-film pattern for wiring is exposed to form a wiring pattern.p
摘要翻译：在半导体衬底上形成第一绝缘膜，第二绝缘膜，第一抗蚀剂图案，蚀刻第二绝缘膜以形成第二绝缘膜图案，在第二绝缘膜上沉积第三绝缘膜形成第三绝缘膜图案，第一绝缘膜被蚀刻以形成第一绝缘膜图案，第四绝缘膜和第二抗蚀剂图案形成在第一绝缘膜图案上，第四绝缘膜被蚀刻以形成第四绝缘膜图案，在第四绝缘膜图案上沉积第五绝缘膜以形成第五绝缘膜图案，蚀刻第一绝缘膜图案的线部分以形成用于布线的第一绝缘膜图案，布线膜形成在用于布线的第一绝缘膜图案上，布线膜被去除，直到用于布线的第一绝缘膜图案暴露以形成布线图案

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