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1. 发明授权

US07768844B2 Nonvolatile semiconductor memory device and method of driving the same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US07768844B2
公开(公告)日：2010-08-03
申请号：US12202601
申请日：2008-09-02
申请人： Satoru Takase , Takuya Futatsuyama
发明人： Satoru Takase , Takuya Futatsuyama
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418
摘要： This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions.
摘要翻译：本公开涉及包括存储单元阵列的存储器，该存储器单元阵列包括沿第一方向延伸的字线，沿与第一方向交叉的第二方向延伸的位线，以及提供分别对应于由该字形成的格子形式的交点的存储单元线和位线; 提供的读出放大器分别对应于位线和读取存储在存储器单元中的数据; 和位线驱动器，当数据被写入存储单元时，位线驱动器被提供给位线并操作位线，其中位线驱动器相对于格子的形式访问与第一存储器单元相对的第一存储器单元，在数据写入操作期间向相邻存储器单元提供数据，而不改变存储在与第一和第二方向上的第一存储单元相邻的存储单元中的数据。

2. 发明授权

US07863751B2 Multilayer wiring structure for memory circuit 有权
标题翻译：存储电路的多层布线结构
公开(公告)号：US07863751B2
公开(公告)日：2011-01-04
申请号：US12171650
申请日：2008-07-11
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H01L29/40
CPC分类号： H01L27/24
摘要： A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s).
摘要翻译：一种半导体集成电路器件，包括：形成有扩散层的半导体衬底; 以及层叠在半导体衬底上方的多层布线，以通过接触插塞连接到扩散层，其中形成在其上的第一布线和第二布线分别经由第一接触插塞和第二接触插塞连接到扩散层，并且排列成并联的第二接触插塞的数量被设定为大于第一接触插塞的数量。

3. 发明授权

US07808854B2 Systems and methods for data transfers between memory cells 有权
标题翻译：存储单元之间数据传输的系统和方法
公开(公告)号：US07808854B2
公开(公告)日：2010-10-05
申请号：US12033198
申请日：2008-02-19
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065 , G11C7/1048 , G11C7/18 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
摘要翻译：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。每个读出放大器被配置为选择性地耦合到数据线。在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器，第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

4. 发明申请

US20090207679A1 Systems and Methods for Data Transfers Between Memory Cells 有权
标题翻译：记忆单元之间数据传输的系统和方法
公开(公告)号：US20090207679A1
公开(公告)日：2009-08-20
申请号：US12033198
申请日：2008-02-19
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C7/065 , G11C7/1048 , G11C7/18 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
摘要翻译：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。每个读出放大器被配置为选择性地耦合到数据线。在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器，第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

5. 发明授权

US07573735B2 Systems and methods for improving memory reliability 失效
标题翻译：提高内存可靠性的系统和方法
公开(公告)号：US07573735B2
公开(公告)日：2009-08-11
申请号：US11530271
申请日：2006-09-08
申请人： Satoru Takase , Takehito Sasaki
发明人： Satoru Takase , Takehito Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C5/143 , G11C5/147
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.
摘要翻译：用于减少由电压之间的相对变化引起的不稳定性和可编写性问题的系统和方法，其中存储单元和访问存储器单元的逻辑组件通过在电压不在可接受的工作范围内时禁止存储器访问而工作。一个实施例包括流水线处理器，其具有在第一电压处接收功率的逻辑部件和以第二电压接收功率的一组SRAM单元。临界条件检测器被配置为监视第一和第二电压并且确定这些电压的比率是否在可接受的范围内。当电压不在可接受范围内时，产生异常，异常处理程序使处理器流水线停止以禁止对SRAM单元的访问。当电压返回到可接受的范围时，异常处理程序将恢复流水线并完成异常的处理。

6. 发明申请

US20080249727A1 Systems and Methods for Determining Variations in Voltages Applied to an Integrated Circuit Chip 审中-公开
标题翻译：确定应用于集成电路芯片的电压变化的系统和方法
公开(公告)号：US20080249727A1
公开(公告)日：2008-10-09
申请号：US11696381
申请日：2007-04-04
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G01R19/00
CPC分类号： G01R31/3012 , G01R31/3004
摘要： Systems and methods for determining local voltages provided by a power distribution network to an integrated circuit chip by applying an external voltage to a power distribution network, firing a set of current sources distributed across the chip and measuring local voltages on the chip. The current sources may, for example, comprise a clock tree carrying a free-running clock signal, or multiple individual current source structures. The voltages may be measured, for instance, by units comprising voltage controlled oscillators (VCO's) coupled to counters which determine the corresponding oscillation frequencies and registers which store the resulting oscillation counts. The measured voltages may be used to identify non-uniformities in the voltage applied across the chip, as well as to determine local differences in the resistance of the power distribution network.
摘要翻译：通过向配电网络施加外部电压来确定由配电网络向集成电路芯片提供的局部电压的系统和方法，点燃分布在芯片上的一组电流源并测量芯片上的局部电压。电流源可以例如包括携带自由运行时钟信号的时钟树，或多个单独的电流源结构。电压可以例如通过耦合到确定相应振荡频率的计数器的压控振荡器（VCO）和存储所得到的振荡计数的寄存器的单元来测量。测量的电压可用于识别施加在芯片上的电压中的不均匀性，以及确定配电网络的电阻的局部差异。

7. 发明申请

US20060267706A1 System and method for configuring conductors within an integrated circuit to reduce impedance variation caused by connection bumps 失效
标题翻译：用于在集成电路内配置导体以减少由连接凸起引起的阻抗变化的系统和方法
公开(公告)号：US20060267706A1
公开(公告)日：2006-11-30
申请号：US11137296
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H01P5/02
CPC分类号： H01L23/64 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01P5/02 , H01L2924/00
摘要： Systems and methods for improved semiconductor device performance are disclosed. In particular, presented are improved semiconductor systems and methods for configuring conductors to reduce impedance variation caused by proximity and/or density and/or operation of connection-bumps. The invention includes adding impedance-reducing conductive features which add no additional functionality to the semiconductor device. The added features may be arranged in areas of sparse connection-bump density. Impedance-reducing conductive features may include metal lines added between functional metal lines, where placement between adjacent functional lines may vary. Impedance-reducing conductive features may be added to any one or combination of conductive layers, and added features may act upon any one or combination of functional features. Further, added features may be electrically active and responsive to semiconductor device operation. Also, methods for determining connection-bump density, which methods may be automated.
摘要翻译：公开了用于改善半导体器件性能的系统和方法。具体地，提出了改进的半导体系统和用于配置导体以减少由接近和/或密度和/或连接凸块的操作引起的阻抗变化的方法。本发明包括增加阻抗减小的导电特征，其不对半导体器件增加额外的功能。附加的特征可以布置在稀疏连接 - 凸起密度的区域中。阻抗减小的导电特征可以包括在功能金属线之间添加的金属线，其中相邻功能线之间的放置可以变化。阻抗减小的导电特征可以被添加到导电层的任何一个或组合，并且附加的特征可以作用于功能特征的任何一个或组合。此外，附加的特征可以是电活动的并且响应于半导体器件操作。另外，用于确定连接凸块密度的方法，哪些方法可以是自动化的。

8. 发明授权

US06674675B2 Semiconductor device with flexible redundancy system 失效
标题翻译：具有灵活冗余系统的半导体器件
公开(公告)号：US06674675B2
公开(公告)日：2004-01-06
申请号：US10348964
申请日：2003-01-23
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.
摘要翻译：存储单元阵列包括用于保存有缺陷单元的备用元件。熔丝组每个都包含有缺陷的地址和指示熔丝组与备用元件之间的关系的映射信息。当缺陷地址与输入地址相匹配时，每个保险丝组输出用于激活相应备用元件的信号。芯片内的熔丝组数量小于备用元件的数量。

9. 发明授权

US06542420B2 Semiconductor device with flexible redundancy system 失效
公开(公告)号：US06542420B2
公开(公告)日：2003-04-01
申请号：US09953307
申请日：2001-09-17
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

10. 发明授权

US5500815A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5500815A
公开(公告)日：1996-03-19
申请号：US981541
申请日：1992-11-25
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/401 , G11C11/404 , G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24 , G11C11/40
CPC分类号： G11C11/565 , G11C11/404 , H01L27/10805
摘要： A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node, and a plurality of MOS transistors which are connected in cascade, a plurality of data storage capacitors, formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.
摘要翻译：半导体存储单元包括形成在半导体衬底上的第一级联栅极，其端部连接到第一节点，以及串联连接的多个MOS晶体管，形成在半导体衬底上的多个数据存储电容器，其每个端部连接到与第一节点相对的相应的一个MOS晶体管的端部，以及形成在存储单元和另一半导体存储单元之间的器件隔离MOS晶体管，它们并排布置在半导体衬底。

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