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    • 3. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060076614A1
    • 2006-04-13
    • US11220678
    • 2005-09-08
    • Hitoshi Ninomiya
    • Hitoshi Ninomiya
    • H01L29/94
    • H01L29/7813H01L29/0634H01L29/1095H01L29/4238H01L29/66734
    • A semiconductor device well balanced between high voltage applicability and low ON resistance, includes an n+-type semiconductor substrate; an n-type drift region formed thereon; a p-type base region formed on the n-type drift region; a plurality of p-type column regions in the n-type drift region so as to contact with the p-type base region and having a predetermined depth in a direction perpendicular to the p-type base region; a plurality of gate electrodes spaced by a regular distance from the centers, as viewed in the depth-wise direction, of each p-type column region, and penetrating the p-type base region, and partly buried in the n-type drift region; n-type source regions provided in the surficial region of the p-type base region around each of the gate electrodes; a drain electrode connected to the back surface of the n+-type semiconductor substrate; and a source electrode connected to the n-type source regions.
    • 在高电压适用性和低导通电阻之间良好平衡的半导体器件包括n + +型半导体衬底; 形成在其上的n型漂移区; 形成在n型漂移区上的p型基区; 在n型漂移区域内的多个p型列区域,以与p型基极区域接触并且在垂直于p型基极区域的方向上具有预定的深度; 多个栅电极,每个p型列区域沿深度方向与中心间隔开一定距离,并且穿透p型基极区域,部分地埋在n型漂移区域中 ; 设置在每个栅电极周围的p型基极区域的表面区域中的n型源极区域; 连接到n + +型半导体衬底的背面的漏电极; 以及与n型源极区域连接的源电极。
    • 4. 发明授权
    • Semiconductor device with vertical MOSFET
    • 具有垂直MOSFET的半导体器件
    • US06639275B2
    • 2003-10-28
    • US10164640
    • 2002-06-10
    • Hitoshi Ninomiya
    • Hitoshi Ninomiya
    • H01L29792
    • H01L29/7813H01L21/823487H01L27/088H01L29/4238H01L29/7811
    • A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that exposes the connection portion of the gate electrode, where the connection portion is located in the trench. The conductive plug is filled in the contact hole of the interlayer dielectric layer in such a way as to contact the connection portion of the gate electrode. The wiring layer is formed on the interlayer dielectric layer in such a way as to contact the plug, resulting in the wiring layer electrically connected to the connection portion by way of the plug. There is no need to form a connection portion for the gate electrode outside of the trench, which means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur.
    • 半导体器件提高了垂直MOSFET的栅极耐受电压,提高了其工作速度。 栅电极形成在第二半导体层的沟槽中。 层间绝缘层具有暴露栅电极的连接部分的接触孔,其中连接部分位于沟槽中。 导电插塞以与栅电极的连接部分接触的方式填充在层间电介质层的接触孔中。 布线层以与接触插塞的方式形成在层间电介质层上,导致布线层通过插头与连接部分电连接。 不需要在沟槽的外部形成用于栅电极的连接部分,这意味着栅极电介质不包括可能发生电介质击穿的弱或更薄的部分。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    • 半导体器件及其制造方法
    • US20080197381A1
    • 2008-08-21
    • US12029478
    • 2008-02-12
    • Yoshiya KawashimaYoshinao MiuraHitoshi Ninomiya
    • Yoshiya KawashimaYoshinao MiuraHitoshi Ninomiya
    • H01L29/04H01L21/336
    • H01L29/7397H01L29/66348
    • A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage. Further, since it is possible that a crystal plane of a channel is the {100} crystal plane, enabling a maximum electron mobility to be obtained, it is possible to increase on-current, so that on-resistance can be reduced.
    • 半导体器件设置有包括具有{110}晶面用作其主表面的N型漂移区的垂直MOSFET,在具有{100}晶面的沟槽中形成的沟槽栅结构,作为 以及设置在N型漂移区域3中的多个P型列区域结构,构成超结结构。 P型列区域结构被布置成在平面图中彼此分离,并且多个列结构中的每一个都包括在横截面中彼此分离的多个第二导电类型的列区域 视图。 通过从垂直于主表面的方向向主表面施加P型掺杂剂的离子注入,P型列区域由于引导而形成在漂移区域中的足够深的位置。 通过这样做,可以获得具有增强的击穿电压的半导体器件。 此外,由于通道的晶面可以是{100}晶面,因此能够获得最大的电子迁移率,可以增加导通电流,从而可以降低导通电阻。
    • 9. 发明授权
    • Semiconductor device, and production method for manufacturing such semiconductor device
    • 半导体装置及其制造方法
    • US07279747B2
    • 2007-10-09
    • US10833055
    • 2004-04-28
    • Hitoshi Ninomiya
    • Hitoshi Ninomiya
    • H01L29/78
    • H01L29/7802H01L29/0634H01L29/0649H01L29/1095H01L29/66712H01L29/7813
    • A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer. A first conductivity type source region is produced in the second conductivity type base region, and both a gate insulating layer and a gate electrode layer are produced so as to be associated with the first conductivity type source region and the first conductivity type drift layer such that an inversion region is defined in the second conductivity type base region in the vicinity of both the gate insulating layer and the gate electrode layer.
    • 半导体器件包括第一导电型半导体衬底。 在第一导电型半导体衬底的表面上形成第一导电型漂移层,并且在第一导电型漂移层中产生第二导电型基极区。 第二导电型基极区域在其表面形成沟槽。 通过用合适的材料填充沟槽和形成在第一导电型漂移层中并位于沟槽填充层下方的第二导电型列区形成沟槽填充层。 在第二导电型基极区域中产生第一导电型源极区域,并且制造栅极绝缘层和栅极电极层,以便与第一导电型源极区域和第一导电型漂移层相关联,使得 在栅极绝缘层和栅极电极层附近的第二导电型基极区域中限定反转区域。