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1. 发明申请

US20050146381A1 BALANCED AMPLIFIER AND FILTER USING THE SAME 失效
标题翻译：使用平衡放大器和滤波器
公开(公告)号：US20050146381A1
公开(公告)日：2005-07-07
申请号：US11059380
申请日：2005-02-17
申请人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul , Krystyna Czarnul
发明人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul , Krystyna Czarnul
IPC分类号： H03F3/45 , H03H11/04
CPC分类号： H03F3/211 , H03F3/45475 , H03F3/45632 , H03F3/45766 , H03F3/45928 , H03F3/45991 , H03F2203/45138 , H03H11/045 , H03H11/32
摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.
摘要翻译：一种平衡放大器，包括一对电压 - 电流转换器，包括第一输入端子，第二输入端子，第一输出端子和第二输出端子，用于将施加到第一输入端子的输入电压转换为从第一输出端子和第二输出端子，其中一个转换器的第二输入端子和第二输出端子连接到另一个转换器的第二输入端子和第二输出端子，以抵消共模元件并提取差分模式组件。

2. 发明申请

US20060006942A1 Balanced amplifier and filter using the same 失效
公开(公告)号：US20060006942A1
公开(公告)日：2006-01-12
申请号：US11221701
申请日：2005-09-09
申请人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul , Krystyna Czarnul
发明人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul , Krystyna Czarnul
IPC分类号： H03F3/45
CPC分类号： H03F3/211 , H03F3/45475 , H03F3/45632 , H03F3/45766 , H03F3/45928 , H03F3/45991 , H03F2203/45138 , H03H11/045 , H03H11/32
摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

3. 发明授权

US06781464B2 Balanced amplifier and filter using the same 失效
标题翻译：平衡放大器和滤波器使用相同
公开(公告)号：US06781464B2
公开(公告)日：2004-08-24
申请号：US10281103
申请日：2002-10-28
申请人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul
发明人： Takeshi Ueno , Tetsuro Itakura , Zdzislaw Czarnul
IPC分类号： H03F345
CPC分类号： H03F3/211 , H03F3/45475 , H03F3/45632 , H03F3/45766 , H03F3/45928 , H03F3/45991 , H03F2203/45138 , H03H11/045 , H03H11/32
摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.
摘要翻译：一种平衡放大器，包括一对电压 - 电流转换器，包括第一输入端子，第二输入端子，第一输出端子和第二输出端子，用于将施加到第一输入端子的输入电压转换为从第一输出端子和第二输出端子，其中一个转换器的第二输入端子和第二输出端子连接到另一个转换器的第二输入端子和第二输出端子，以抵消共模元件并提取差分模式组件。

4. 发明申请

US20110235367A1 DC TO DC CONVERTER 有权
标题翻译：直流到直流转换器
公开(公告)号：US20110235367A1
公开(公告)日：2011-09-29
申请号：US12878271
申请日：2010-09-09
申请人： Takeshi Ueno , Tetsuro Itakura
发明人： Takeshi Ueno , Tetsuro Itakura
IPC分类号： H02M3/24
CPC分类号： H02M3/1563
摘要： A DC to DC converter includes an input terminal, an output terminal, first and second switches, an inductor, a smoothing unit, a first impedance element, a first resistor element, an operational amplifier and a control unit. The first switch is connected to the input terminal. The second switch is connected to the first switch and a ground terminal. The inductor is connected to the first switch and the output terminal. The smoothing unit is connected to the inductor and the ground terminal. The first impedance element is connected to the smoothing unit. The first resistor element is connected in series with the first impedance element. The operational amplifier is connected to the first impedance element. Reference voltage is added to the operational amplifier. The control unit controls the first and second switches according to a control signal outputted from the operational amplifier.
摘要翻译： DC-DC转换器包括输入端子，输出端子，第一和第二开关，电感器，平滑单元，第一阻抗元件，第一电阻元件，运算放大器和控制单元。第一个开关连接到输入端。第二开关连接到第一开关和接地端子。电感器连接到第一开关和输出端子。平滑单元连接到电感器和接地端子。第一阻抗元件连接到平滑单元。第一电阻元件与第一阻抗元件串联连接。运算放大器连接到第一阻抗元件。参考电压加到运算放大器上。控制单元根据从运算放大器输出的控制信号来控制第一和第二开关。

5. 发明授权

US07679428B2 Comparator and analog-to-digital converter using the same 失效
标题翻译：比较器和模数转换器使用相同
公开(公告)号：US07679428B2
公开(公告)日：2010-03-16
申请号：US12175209
申请日：2008-07-17
申请人： Mai Nozawa , Daisuke Kurose , Takeshi Ueno , Tetsuro Itakura
发明人： Mai Nozawa , Daisuke Kurose , Takeshi Ueno , Tetsuro Itakura
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K5/249
摘要： A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal.
摘要翻译：比较器包括插入在电源端子和第一可变电阻器的一端之间的第一反相器，包括：第一FinFET，其具有用于接收正相输出信号的第一栅极端子和用于接收时钟的第二栅极端子信号在第一电平和第二电平之间变化，使正相输出信号反相，并输出负相输出信号，并且插入在电源端和第二可变电阻的一端之间的第二反相器包括第二 FinFET具有用于接收负相输出信号的第三栅极端子，用于接收时钟信号的第四栅极端子和与第一FinFET相同的极性，反相负相输出信号，并输出正相输出信号。

6. 发明授权

US09225168B2 Switching power supply device and control circuit thereof 有权
标题翻译：开关电源装置及其控制电路
公开(公告)号：US09225168B2
公开(公告)日：2015-12-29
申请号：US13692044
申请日：2012-12-03
申请人： Taichi Ogawa , Takeshi Ueno , Tetsuro Itakura
发明人： Taichi Ogawa , Takeshi Ueno , Tetsuro Itakura
IPC分类号： H02J1/00 , H02M3/158 , H02M3/156
CPC分类号： H02J1/00 , H02M3/158 , H02M2003/1566 , Y10T307/549
摘要： A control circuit of a switching power supply device has a first current source capable of supplying an auxiliary current to a load resistance of the switching power supply device when a load current flowing through the load resistance increases, a second current source capable of pulling in a current from the load resistance when the load current flowing through the load resistance decreases, and an auxiliary current controller configured to activate the first current source or the second current source from when a variation in the load current flowing through the load resistance is detected to have exceeded a predetermined level until a current flowing through the inductor becomes equal to the current flowing through the load resistance.
摘要翻译：开关电源装置的控制电路具有第一电流源，当流过负载电阻的负载电流增加时能够向开关电源装置的负载电阻提供辅助电流，第二电流源能够拉入当负载电流流过负载电阻的负载电流下降时，负载电阻的电流以及从流过负载电阻的负载电流的变化检测到的第一电流源或第二电流源的辅助电流控制器被配置为具有超过预定电平，直到流过电感器的电流变得等于流过负载电阻的电流。

7. 发明授权

US08604766B2 DC-DC converter and control circuit thereof 失效
标题翻译： DC-DC转换器及其控制电路
公开(公告)号：US08604766B2
公开(公告)日：2013-12-10
申请号：US13692010
申请日：2012-12-03
申请人： Kei Shiraishi , Takeshi Ueno , Taichi Ogawa , Tetsuro Itakura
发明人： Kei Shiraishi , Takeshi Ueno , Taichi Ogawa , Tetsuro Itakura
IPC分类号： G05F1/59
CPC分类号： G05F1/468 , H02M3/157 , H02M2003/1566
摘要： A control circuit of a DC-DC converter has a voltage difference signal generator configured to generate a digital voltage difference signal depending on a voltage difference between the output voltage and a reference voltage, a PID controller configured to generate a digital PID signal for determining the duty ratio of the pulse-width modulated signal, based on the digital voltage difference signal, a phase controller configured to generate a digital phase control signal for determining a phase of the pulse-width modulated signal, based on the digital voltage difference signal, and a PWM generator configured to generate the pulse-width modulated signal, based on the digital PID signal and the digital phase control signal.
摘要翻译： DC-DC转换器的控制电路具有：电压差信号发生器，被配置为根据输出电压和参考电压之间的电压差产生数字电压差信号; PID控制器，被配置为产生数字PID信号以确定基于数字电压差信号的脉宽调制信号的占空比;相位控制器，被配置为基于数字电压差信号产生用于确定脉宽调制信号的相位的数字相位控制信号;以及 PWM发生器，被配置为基于数字PID信号和数字相位控制信号来产生脉宽调制信号。

8. 发明授权

US08410762B2 DC-DC converter 有权
标题翻译： DC-DC转换器
公开(公告)号：US08410762B2
公开(公告)日：2013-04-02
申请号：US13306119
申请日：2011-11-29
申请人： Takeshi Ueno , Tetsuro Itakura
发明人： Takeshi Ueno , Tetsuro Itakura
IPC分类号： G05F1/613 , G05F1/40
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： The high-side switch has one end connected to the input terminal. The low-side switch has one end connected to other end of the high-side switch and other end connected to a ground terminal. The inductor has one end connected to the other end of the high-side switch and other end connected to the output terminal. The capacitor has one end connected to the other end of the inductor and other end connected to the ground terminal. The high-side switch controlling circuit generates and supplies a high-side switch controlling signal based on a target voltage of the output terminal, the output voltage of the output terminal, and a current flowing through the capacitor, to the high-side switch. The low-side switch controlling circuit generates and supplies a low-side switch controlling signal based on the high-side switch controlling signal and a current flowing through the inductor, to the low-side switch.
摘要翻译：高边开关的一端连接到输入端。低侧开关的一端连接到高侧开关的另一端，另一端连接到接地端子。电感器的一端连接到高侧开关的另一端，另一端连接到输出端子。电容器的一端连接到电感器的另一端，另一端连接到接地端子。高侧开关控制电路基于输出端子的目标电压，输出端子的输出电压和流过电容器的电流产生并提供高侧开关控制信号到高侧开关。低侧开关控制电路基于高侧开关控制信号和流过电感器的电流产生并提供低侧开关控制信号到低侧开关。

9. 发明申请

US20090045995A1 COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER USING THE SAME 失效
标题翻译：使用相同的比较器和模拟数字转换器
公开(公告)号：US20090045995A1
公开(公告)日：2009-02-19
申请号：US12175209
申请日：2008-07-17
申请人： Mai NOZAWA , Daisuke Kurose , Takeshi Ueno , Tetsuro Itakura
发明人： Mai NOZAWA , Daisuke Kurose , Takeshi Ueno , Tetsuro Itakura
IPC分类号： H03M1/34
CPC分类号： H03K5/2481 , H03K5/249
摘要： A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal.
摘要翻译：比较器包括插入在电源端子和第一可变电阻器的一端之间的第一反相器，包括：第一FinFET，其具有用于接收正相输出信号的第一栅极端子和用于接收时钟的第二栅极端子信号在第一电平和第二电平之间变化，使正相输出信号反相，并输出负相输出信号，并且插入在电源端和第二可变电阻的一端之间的第二反相器包括第二 FinFET具有用于接收负相输出信号的第三栅极端子，用于接收时钟信号的第四栅极端子和与第一FinFET相同的极性，反相负相输出信号，并输出正相输出信号。

10. 发明申请

US20070011482A1 Clock generator, radio receiver using the same, function system, and sensing system 审中-公开
标题翻译：时钟发生器，使用相同的无线电接收器，功能系统和传感系统
公开(公告)号：US20070011482A1
公开(公告)日：2007-01-11
申请号：US11438589
申请日：2006-05-22
申请人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji , Tetsuro Itakura
发明人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji , Tetsuro Itakura
IPC分类号： G06F1/00
CPC分类号： H03L7/23 , H03L7/18
摘要： A clock generator having phase locked loops to receive reference signals from a shared reference signal source and generate clock signals differing in frequency, respectively, includes a phase comparator which generates a voltage signal in response to a phase difference between a phase of the reference signal and a phase of a feedback signal, a VCO controlled by a voltage signal from the phase comparator, and a frequency divider group connected in cascade in a feedback loop between an output of the VCO and an input of a feedback signal, and takes out a clock signals from each output of the frequency divider group.
摘要翻译：具有锁相环的时钟发生器分别接收来自共享参考信号源的参考信号并且分别产生频率不同的时钟信号，该相位比较器响应于参考信号的相位和相位差之间的相位差产生电压信号反馈信号的相位，由来自相位比较器的电压信号控制的VCO和在VCO的输出与反馈信号的输入之间的反馈回路中级联连接的分频器组，并且取出时钟来自分频器组的每个输出的信号。

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