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    • 5. 发明授权
    • Digital key telephone set and digital key telephone system
    • 数字钥匙电话机和数字电话系统
    • US06807261B2
    • 2004-10-19
    • US09939757
    • 2001-08-28
    • Toshiaki TakahashiToshiaki TanakaTakeshi Horiuchi
    • Toshiaki TakahashiToshiaki TanakaTakeshi Horiuchi
    • H04M100
    • H04M9/002H04L7/044
    • A clock generating circuit generates a clock of a rate corresponding to a Dch rate in response to a specification from the exterior. A counting circuit detects completion of reception of one frame by counting the clock number up to “11” at timing at which a start bit detecting circuit detects a start bit in a serial signal. An S/P converting circuit fetches a serial Dch signal bit by bit in synchronism with the clock, outputs the latest fetched 10 bits in a parallel form and latches eight bits of a real data portion among the output data into a latch circuit at the time when reception of one frame is completed. In parallel with the above operation, a parity calculating circuit and flag/interruption generating circuit set various flags and generate a reception completion interruption.
    • 时钟发生电路响应于来自外部的规格,生成对应于Dch速率的速率的时钟。 在起始位检测电路检测到串行信号中的起始位的定时,计数电路通过对时钟数高达“11”来检测一帧的接收完成。 S / P转换电路与时钟同步地逐行取出串行Dch信号,以并行形式输出最新提取的10位,并将输出数据中的8位实数数据部分锁存在锁存电路中 当一帧的接收完成时。 与上述操作并行,奇偶校验计算电路和标志/中断产生电路设置各种标志并产生接收完成中断。