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1. 发明授权

US07032066B2 Semiconductor memory unit 有权
公开(公告)号：US07032066B2
公开(公告)日：2006-04-18
申请号：US09956346
申请日：2001-09-20
申请人： Takeo Miki , Mikio Asakura , Takeshi Hamamoto
发明人： Takeo Miki , Mikio Asakura , Takeshi Hamamoto
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C7/10 , G11C7/1066 , G11C11/4093
摘要： In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

2. 发明授权

US6064607A Semiconductor memory device with predecoder 有权
标题翻译：具有预解码器的半导体存储器件
公开(公告)号：US6064607A
公开(公告)日：2000-05-16
申请号：US177484
申请日：1998-10-23
申请人： Takeo Miki , Mikio Asakura , Satoshi Kawasaki
发明人： Takeo Miki , Mikio Asakura , Satoshi Kawasaki
IPC分类号： G11C8/10 , G11C29/00 , G11C7/00
CPC分类号： G11C29/80 , G11C8/10
摘要： Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.
摘要翻译：第一和第二编程电路中的每一个包括确定节点，第一至第四保险丝，第一至第四N沟道MOS晶体管和第一至第四电源线。第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。因此，可以减少行地址预解码信号线的互连电容。此外，可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸，以允许整个芯片的布局面积较小。

3. 发明申请

US20050088871A1 Semiconductor device and method of inspecting the same 失效
标题翻译：半导体装置及其检查方法
公开(公告)号：US20050088871A1
公开(公告)日：2005-04-28
申请号：US10988710
申请日：2004-11-16
申请人： Takeo Miki , Takeshi Hamamoto
发明人： Takeo Miki , Takeshi Hamamoto
IPC分类号： G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3181 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C29/12 , G11C29/50 , G11C29/56 , G11C11/22
CPC分类号： G11C29/50012 , G01R31/3016 , G01R31/31701 , G01R31/3181 , G11C7/1063 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C2029/5002 , G11C2207/105
摘要： A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.
摘要翻译：除了实现正常操作的集成电路之外，半导体芯片还设置有相位比较电路（1）。相位比较电路（1）比较集成电路的内部信号（A）和外部信号之间的相位，并从半导体芯片向外输出表示该比较结果的监视信号（MONSIG）。因此，可以直接检测集成电路的内部信号（A）的相位。

4. 发明授权

US07023198B2 Semiconductor device and method of inspecting the same 失效
标题翻译：半导体装置及其检查方法
公开(公告)号：US07023198B2
公开(公告)日：2006-04-04
申请号：US10988710
申请日：2004-11-16
申请人： Takeo Miki , Takeshi Hamamoto
发明人： Takeo Miki , Takeshi Hamamoto
IPC分类号： G01R25/00
CPC分类号： G11C29/50012 , G01R31/3016 , G01R31/31701 , G01R31/3181 , G11C7/1063 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C2029/5002 , G11C2207/105
摘要： A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.
摘要翻译：除了实现正常操作的集成电路之外，半导体芯片还设置有相位比较电路（1）。相位比较电路（1）比较集成电路的内部信号（A）和外部信号之间的相位，并从半导体芯片向外输出表示该比较结果的监视信号（MONSIG）。因此，可以直接检测集成电路的内部信号（A）的相位。

5. 发明授权

US06833723B2 Semiconductor device with phase comparator comparing phases between internal signal and external signal 失效
标题翻译：具有相位比较器的半导体器件比较内部信号和外部信号之间的相位
公开(公告)号：US06833723B2
公开(公告)日：2004-12-21
申请号：US09906724
申请日：2001-07-18
申请人： Takeo Miki , Takeshi Hamamoto
发明人： Takeo Miki , Takeshi Hamamoto
IPC分类号： G01R3102
CPC分类号： G11C29/50012 , G01R31/3016 , G01R31/31701 , G01R31/3181 , G11C7/1063 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C2029/5002 , G11C2207/105
摘要： A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.
摘要翻译：除了实现正常操作的集成电路之外，半导体芯片还设置有相位比较电路（1）。相位比较电路（1）比较集成电路的内部信号（A）和外部信号之间的相位，并从半导体芯片向外输出表示该比较结果的监视信号（MONSIG）。因此，可以直接检测集成电路的内部信号（A）的相位。

6. 发明授权

US06757212B2 Clock synchronous type semiconductor memory device 有权
标题翻译：时钟同步型半导体存储器件
公开(公告)号：US06757212B2
公开(公告)日：2004-06-29
申请号：US10034544
申请日：2002-01-03
申请人： Takeshi Hamamoto , Takeo Miki
发明人： Takeshi Hamamoto , Takeo Miki
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/222
摘要： A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.
摘要翻译：通过利用具有取决于内部时钟信号的工作频率的延迟时间的延迟电路产生的时钟信号被施加到第一电路以激活它，以及时钟信号，其具有不依赖于时钟频率并相对于外部时钟信号被同相调节，被施加到接收第一电路的输出信号以用于其操作的第二电路。因此，可以将第二电路的操作定时设置为尽可能晚。因此，可以减轻第一电路的操作条件，以实现高速数据传输。即使在高速运行中，内部数据也可以被可靠地接收并准确传送。

7. 发明授权

US08314970B2 Image processing apparatus, image processing method, image forming apparatus, image forming method, and recorded material 有权
标题翻译：图像处理装置，图像处理方法，图像形成装置，图像形成方法和记录材料
公开(公告)号：US08314970B2
公开(公告)日：2012-11-20
申请号：US12163041
申请日：2008-06-27
申请人： Takeo Miki , Takashi Yamaguchi , Kenji Miyazaki
发明人： Takeo Miki , Takashi Yamaguchi , Kenji Miyazaki
IPC分类号： H04N1/405
CPC分类号： H04N1/32309 , H04N1/32208 , H04N1/32251 , H04N1/32256 , H04N1/32267 , H04N1/32293
摘要： An image processing apparatus according to an embodiment of the invention, includes an image input unit which inputs main image information defined by first, second and third color component information corresponding to at least three colors, a modulation unit which modulates a color difference grid pattern by sub information, a superposing unit which superposes the modulated color difference grid pattern on each of the first, second and third color component information after the modulated color difference grid pattern and each of the first, second and third color component information are rotated relative to each other through a predetermined angle, and a composition unit which composites the first, second and third color component information to generate color image information.
摘要翻译：根据本发明的实施例的图像处理装置包括：图像输入单元，其输入由至少三种颜色对应的第一，第二和第三颜色分量信息定义的主图像信息;调制单元，其通过子信息，叠加单元，其在调制色差网格图案之后将调制色差网格图案叠加在第一，第二和第三颜色分量信息中的每一个上，并且第一，第二和第三颜色分量信息中的每一个相对于每个颜色分量信息旋转另一个通过预定角度，以及合成单元，其合成第一，第二和第三颜色分量信息以生成彩色图像信息。

8. 发明授权

US08175323B2 Image processing method and image processing apparatus 有权
标题翻译：图像处理方法和图像处理装置
公开(公告)号：US08175323B2
公开(公告)日：2012-05-08
申请号：US12190798
申请日：2008-08-13
申请人： Takashi Yamaguchi , Takeo Miki , Kenji Miyazaki
发明人： Takashi Yamaguchi , Takeo Miki , Kenji Miyazaki
IPC分类号： G06K9/00
CPC分类号： G06T1/0028 , G06T2201/0051 , G06T2201/0061 , G06T2201/0083 , H04N1/32272 , H04N1/32283 , H04N1/32309
摘要： In an image processing apparatus for creating synthetic image information by embedding sub-information in an invisible state in main image information in a visible state, attention pixels in the main image information are set, a specific pixel block is created by assigning a first specific pixel to the attention pixel of a first color and a second specific pixel to the attention pixel of a second color, first key information is selected for a first value of the sub-information constituted by binary information and second key information is selected for a second value, color difference modulation processing is performed on the selected key information based on a predetermined color difference amount, and the color-difference-modulated key information is superposed on the specific pixel block to thereby create the synthetic image information in which the sub-information in an invisible state is embedded in the main image information.
摘要翻译：在用于通过以可见状态将主要图像信息中的不可见状态嵌入子信息来创建合成图像信息的图像处理装置中，设置主图像信息中的注意像素，通过分配第一特定像素来创建特定像素块将第一颜色和第二特定像素的关注像素注视到第二颜色的关注像素，对于由二进制信息构成的子信息的第一值选择第一密钥信息，并且为第二值选择第二密钥信息基于预定的色差量对所选择的密钥信息执行色差调制处理，并且将色差调制密钥信息叠加在特定像素块上，从而创建合成图像信息，其中子信息在主图像信息中嵌入一个隐形状态。

9. 发明申请

US20120027264A1 IMAGE PROCESSING METHOD AND IMAGE PROCESSING APPARATUS 有权
标题翻译：图像处理方法和图像处理装置
公开(公告)号：US20120027264A1
公开(公告)日：2012-02-02
申请号：US13151888
申请日：2011-06-02
申请人： Takashi Yamaguchi , Takeo Miki , Kenji Miyazaki
发明人： Takashi Yamaguchi , Takeo Miki , Kenji Miyazaki
IPC分类号： G06K9/00
CPC分类号： H04N1/32309 , G03G15/507 , G03G21/043 , H04N1/00005 , H04N1/00015 , H04N1/00023 , H04N1/00031 , H04N1/00047 , H04N1/0005 , H04N1/00063 , H04N1/00076 , H04N1/29 , H04N1/3216
摘要： According to one embodiment, an image processing method for inspecting an image includes creating synthetic image information in which information is synthesized with main image information in a visible state which the human eyes perceive in an invisible state which is hard to perceive with the human eyes, printing the synthetic image information onto a medium, acquiring an image printed on the medium as an inspection image information, extracting information embedded in the main image information from the inspection image acquired, and determining a fault in the image printed on the medium based on an extraction result of information.
摘要翻译：根据一个实施例，用于检查图像的图像处理方法包括创建合成图像信息，其中以与人眼难以察觉的看不见状态的人眼察觉的可见状态的主图像信息合成信息，将合成图像信息打印到介质上，获取作为检查图像信息的打印在介质上的图像，从获取的检查图像中提取嵌入在主图像信息中的信息，以及基于打印在介质上的图像中的故障来确定提取结果信息。

10. 发明申请

US20100139457A1 METHOD AND APPARATUS FOR RECOVERING INDIUM FROM ETCHING WASTE SOLUTION CONTAINING INDIUM AND FERRIC CHLORIDE 失效
标题翻译：用于回收含有腐蚀性和氯化铬的废物溶液的方法和装置
公开(公告)号：US20100139457A1
公开(公告)日：2010-06-10
申请号：US12524170
申请日：2007-11-19
申请人： Takeo Miki , Tamotsu Sugimoto , Eiichi Sahashi , Takamichi Honma , Tomoharu Maeseto
发明人： Takeo Miki , Tamotsu Sugimoto , Eiichi Sahashi , Takamichi Honma , Tomoharu Maeseto
IPC分类号： C22B58/00
CPC分类号： C22B3/46 , C22B7/006 , C22B58/00 , Y02P10/234
摘要： It is an object to provide a method and an apparatus for recovering indium, the method and apparatus ensuring that it is unnecessary to recover indium in the form of indium hydroxide, indium can be recovered easily by a filter or the like without handling inferiors and also, the recovery rate of indium is greatly improved. The method includes immersing a precipitation-inducing metal which includes zinc and is made into the form of a solid such that any part coming into view three-dimensionally has a longitudinal length of 2.5 to 10 mm in an etching waste solution containing at least indium and ferric chloride and allowed to stand, thereby allowing indium contained in the etching waste solution to precipitate on the surface of the precipitation-inducing metal based on a difference in ionization tendency between zinc and indium, and detaching the indium precipitated on the surface of the precipitation-inducing metal to recover it.
摘要翻译：本发明的目的是提供一种用于回收铟的方法和装置，该方法和装置确保不需要以铟氢氧化物的形式回收铟，铟可以通过过滤器等容易地回收而不处理下层，还可以，铟的回收率大大提高。该方法包括将包含锌的沉淀诱导金属浸渍并制成固体形式，使得在至少含有铟的蚀刻废液中三维地观察到的纵向长度为2.5至10mm的任何部分，以及使其静置，由此使蚀刻废液中所含的铟基于锌和铟之间的离子化倾向的差异沉淀在沉淀诱导金属的表面上，并且分离沉淀在沉淀表面上的铟诱导金属回收。

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