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    • 1. 发明授权
    • Semiconductor memory device with predecoder
    • 具有预解码器的半导体存储器件
    • US6064607A
    • 2000-05-16
    • US177484
    • 1998-10-23
    • Takeo MikiMikio AsakuraSatoshi Kawasaki
    • Takeo MikiMikio AsakuraSatoshi Kawasaki
    • G11C8/10G11C29/00G11C7/00
    • G11C29/80G11C8/10
    • Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.
    • 第一和第二编程电路中的每一个包括确定节点,第一至第四保险丝,第一至第四N沟道MOS晶体管和第一至第四电源线。 第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。 包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。 第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。 同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。 因此,可以减少行地址预解码信号线的互连电容。 此外,可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸,以允许整个芯片的布局面积较小。
    • 4. 发明授权
    • Image processing method and image processing apparatus
    • 图像处理方法和图像处理装置
    • US08175323B2
    • 2012-05-08
    • US12190798
    • 2008-08-13
    • Takashi YamaguchiTakeo MikiKenji Miyazaki
    • Takashi YamaguchiTakeo MikiKenji Miyazaki
    • G06K9/00
    • G06T1/0028G06T2201/0051G06T2201/0061G06T2201/0083H04N1/32272H04N1/32283H04N1/32309
    • In an image processing apparatus for creating synthetic image information by embedding sub-information in an invisible state in main image information in a visible state, attention pixels in the main image information are set, a specific pixel block is created by assigning a first specific pixel to the attention pixel of a first color and a second specific pixel to the attention pixel of a second color, first key information is selected for a first value of the sub-information constituted by binary information and second key information is selected for a second value, color difference modulation processing is performed on the selected key information based on a predetermined color difference amount, and the color-difference-modulated key information is superposed on the specific pixel block to thereby create the synthetic image information in which the sub-information in an invisible state is embedded in the main image information.
    • 在用于通过以可见状态将主要图像信息中的不可见状态嵌入子信息来创建合成图像信息的图像处理装置中,设置主图像信息中的注意像素,通过分配第一特定像素来创建特定像素块 将第一颜色和第二特定像素的关注像素注视到第二颜色的关注像素,对于由二进制信息构成的子信息的第一值选择第一密钥信息,并且为第二值选择第二密钥信息 基于预定的色差量对所选择的密钥信息执行色差调制处理,并且将色差调制密钥信息叠加在特定像素块上,从而创建合成图像信息,其中子信息 在主图像信息中嵌入一个隐形状态。
    • 8. 发明授权
    • Semiconductor memory device driven with low voltage
    • 半导体存储器件采用低电压驱动
    • US07102935B2
    • 2006-09-05
    • US10972537
    • 2004-10-26
    • Takeo MikiYasuhiko TsukikawaShinji Tanaka
    • Takeo MikiYasuhiko TsukikawaShinji Tanaka
    • G11C5/14G11C7/00G11C8/00
    • G11C11/4074G11C5/14
    • Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.
    • 分别为列解码器,阵列相关电路和列解码器之外的外围电路提供独立电源系统,从而产生外围电源电压,阵列电源电压和列解码器电源电压 彼此独立地分别作为工作电源电压提供给外围电路,阵列相关电路和列解码器。 优选地,正常操作期间的列解码器电源电压被设置为外围电源电压和阵列电源电压之间的中间电压。 因此,可以获得适于驱动具有低电压的晶体管以实现更低功耗的阵列配置。