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1. 发明授权

US08891318B2 Semiconductor device having level shift circuit 有权
标题翻译：具有电平移位电路的半导体器件
公开(公告)号：US08891318B2
公开(公告)日：2014-11-18
申请号：US13286665
申请日：2011-11-01
申请人： Takenori Sato , Yoji Idei , Hiromasa Noda
发明人： Takenori Sato , Yoji Idei , Hiromasa Noda
IPC分类号： G11C7/10 , G11C7/22 , H03K19/0175 , G11C11/4076 , G11C29/02 , H03K3/356 , G11C29/50 , G11C11/4093
CPC分类号： G11C11/4093 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , H03K3/356104
摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
摘要翻译：半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

2. 发明申请

US20120134439A1 SEMICONDUCTOR DEVICE HAVING LEVEL SHIFT CIRCUIT 有权
标题翻译：具有电平转换电路的半导体器件
公开(公告)号：US20120134439A1
公开(公告)日：2012-05-31
申请号：US13286665
申请日：2011-11-01
申请人： Takenori Sato , Yoji Idei , Hiromasa Noda
发明人： Takenori Sato , Yoji Idei , Hiromasa Noda
IPC分类号： H04L27/00 , H03K19/0175 , H03L5/00
CPC分类号： G11C11/4093 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , H03K3/356104
摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
摘要翻译：半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

3. 发明授权

US08659321B2 Semiconductor device having sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US08659321B2
公开(公告)日：2014-02-25
申请号：US13306560
申请日：2011-11-29
申请人： Yuko Watanabe , Yoshiro Riho , Hiromasa Noda , Yoji Idei , Kosuke Goto
发明人： Yuko Watanabe , Yoshiro Riho , Hiromasa Noda , Yoji Idei , Kosuke Goto
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C7/222 , G11C11/4074 , G11C11/4076
摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
摘要翻译：半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及用于控制第一至第三驱动器电路的操作的定时控制电路。定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为基于第一和第二延迟电路的延迟量的总和来决定。

4. 发明申请

US20090016126A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090016126A1
公开(公告)日：2009-01-15
申请号：US12170561
申请日：2008-07-10
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50008 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.
摘要翻译：提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。选择晶体管设置在位线和读出放大器电路之间。包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

5. 发明授权

US07719911B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07719911B2
公开(公告)日：2010-05-18
申请号：US12169873
申请日：2008-07-09
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C7/08 , G11C11/4091
摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.
摘要翻译：提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

6. 发明申请

US20090016139A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20090016139A1
公开(公告)日：2009-01-15
申请号：US12169873
申请日：2008-07-09
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/08 , G11C11/4091
摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.
摘要翻译：提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

7. 发明授权

US07649790B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07649790B2
公开(公告)日：2010-01-19
申请号：US12170561
申请日：2008-07-10
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50008 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.
摘要翻译：提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。选择晶体管设置在位线和读出放大器电路之间。包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

8. 发明授权

US08174907B2 Semiconductor device having data input/output unit connected to bus line 有权
标题翻译：具有连接到总线的数据输入/输出单元的半导体器件
公开(公告)号：US08174907B2
公开(公告)日：2012-05-08
申请号：US12763741
申请日：2010-04-20
申请人： Takuyo Kodama , Yoji Idei
发明人： Takuyo Kodama , Yoji Idei
IPC分类号： G11C7/10
CPC分类号： G11C11/4094 , G11C7/1006 , G11C7/1012 , G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.
摘要翻译：提供一种半导体器件，包括：第一和第二总线; 连接在第一和第二总线之间的第一缓冲器; 连接到第一总线的第二和第三缓冲器; 连接到第二总线的第四和第五缓冲器; 经由第一，第二和第三缓冲器连接到第二总线的第一至第四组; 经由第四和第五缓冲器连接到第二总线的第五至第八组; 以及连接到第二总线的数据输入/输出单元。第四和第五缓冲器的传输延迟时间长于第一，第二和第三缓冲器的传输延迟时间。由此，可以消除由于近端和近端之间的距离的差异导致的数据传输时间的差异，而不会导致线密度的显着增加，功率消耗的增加等。

9. 发明授权

US07889584B2 Semiconductor memory device having input first-stage circuit 有权
标题翻译：具有输入第一级电路的半导体存储器件
公开(公告)号：US07889584B2
公开(公告)日：2011-02-15
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： G11C7/02
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

10. 发明授权

US07675347B2 Semiconductor device operating in an active mode and a standby mode 失效
标题翻译：半导体器件工作在主动模式和待机模式
公开(公告)号：US07675347B2
公开(公告)日：2010-03-09
申请号：US11984464
申请日：2007-11-19
申请人： Kazuhiro Teramoto , Yoji Idei
发明人： Kazuhiro Teramoto , Yoji Idei
IPC分类号： H03K3/01
CPC分类号： H03K3/356113 , H03K19/0016 , H03K2217/0018
摘要： A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.
摘要翻译：半导体器件以活动模式或待机模式工作，并且包括提供在待机模式下比在活动模式中更高的衬底电位的衬底电位电源线以及提供源的源极 - 电位电源线待机模式下的电位低于活动模式。在从待机模式切换到激活模式的模式期间，电位均衡晶体管导通以使从衬底电位电源线流到源极电源线的电流通过，以减少移位所需的时间长度从待机模式到活动模式。

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