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1. 发明授权

US07167352B2 Multilayer chip varistor 有权
标题翻译：多层芯片压敏电阻
公开(公告)号：US07167352B2
公开(公告)日：2007-01-23
申请号：US11137584
申请日：2005-05-26
申请人： Dai Matsuoka , Katsunari Moriai , Takehiko Abe , Koichi Ishii
发明人： Dai Matsuoka , Katsunari Moriai , Takehiko Abe , Koichi Ishii
IPC分类号： H01G4/228
CPC分类号： H01C7/18 , H01C7/1006
摘要： A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.
摘要翻译：多层片式压敏电阻器包括形成在多层体上的多层体和一对外部电极。多层体具有变阻器部和设置成插入所述可变电阻部的一对外层部。变阻器部分包括显影电压非线性特性的变阻器层和设置成插入可变电阻层的一对内部电极。一对外部电极连接到该对内部电极的各个电极。将外层部分的相对介电常数设定为低于可变电阻层中的一对内部电极彼此重叠的区域的相对介电常数。

2. 发明申请

US20050276001A1 Multilayer chip varistor 有权
标题翻译：多层芯片压敏电阻
公开(公告)号：US20050276001A1
公开(公告)日：2005-12-15
申请号：US11137584
申请日：2005-05-26
申请人： Dai Matsuoka , Katsunari Moriai , Takehiko Abe , Koichi Ishii
发明人： Dai Matsuoka , Katsunari Moriai , Takehiko Abe , Koichi Ishii
IPC分类号： H01C7/10 , H01C7/18 , H01G4/228
CPC分类号： H01C7/18 , H01C7/1006
摘要： A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.
摘要翻译：多层片式压敏电阻器包括形成在多层体上的多层体和一对外部电极。多层体具有变阻器部和设置成插入所述可变电阻部的一对外层部。变阻器部分包括显影电压非线性特性的变阻器层和设置成插入可变电阻层的一对内部电极。一对外部电极连接到该对内部电极的各个电极。将外层部分的相对介电常数设定为低于可变电阻层中的一对内部电极彼此重叠的区域的相对介电常数。

3. 外观设计

USD290345S Carton 失效
公开(公告)号：USD290345S
公开(公告)日：1987-06-16
申请号：US659335
申请日：1984-10-10
申请人： Takehiko Abe
设计人： Takehiko Abe

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