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1. 发明申请

US20080238632A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080238632A1
公开(公告)日：2008-10-02
申请号：US12057671
申请日：2008-03-28
申请人： Takefumi ENDO , Takayuki Tsukamoto
发明人： Takefumi ENDO , Takayuki Tsukamoto
IPC分类号： H04B7/00
CPC分类号： H04B5/02 , H04B5/0031 , H04B5/0037
摘要： In an IC tag, when a semiconductor integrated circuit device is activated, an operation control unit sets existence/nonexistence of a communication distance limitation for reducing a communication distance to a state management unit. If the communication distance limitation is not set, a switch unit is turned ON and a demodulated command is inputted from a command demodulation circuit to a command decode unit. If the communication distance limitation is set, a power intensity monitor unit judges whether the power of a rectification circuit is a predetermined arbitrary field intensity or more. If the power is smaller than the predetermined arbitrary field intensity, the switch unit is turned OFF and various commands demodulated by the command demodulation circuit are not inputted to the command decode unit. As a result, the semiconductor integrated circuit device does not operate.
摘要翻译：在IC标签中，当半导体集成电路器件被激活时，操作控制单元设置存在/不存在通信距离限制，以减少与状态管理单元的通信距离。如果没有设定通信距离限制，则开关单元被接通，并且解调命令从命令解调电路输入到命令解码单元。如果设置了通信距离限制，则功率强度监视单元判定整流电路的功率是否为预定的任意场强度以上。如果功率小于预定的任意场强，则切换单元关闭，并且由命令解调电路解调的各种命令不被输入到命令解码单元。结果，半导体集成电路器件不工作。

2. 发明授权

US08138893B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08138893B2
公开(公告)日：2012-03-20
申请号：US12057671
申请日：2008-03-28
申请人： Takefumi Endo , Takayuki Tsukamoto
发明人： Takefumi Endo , Takayuki Tsukamoto
IPC分类号： H04Q5/22
CPC分类号： H04B5/02 , H04B5/0031 , H04B5/0037
摘要： In an IC tag, when a semiconductor integrated circuit device is activated, an operation control unit sets existence/nonexistence of a communication distance limitation for reducing a communication distance to a state management unit. If the communication distance limitation is not set, a switch unit is turned ON and a demodulated command is inputted from a command demodulation circuit to a command decode unit. If the communication distance limitation is set, a power intensity monitor unit judges whether the power of a rectification circuit is greater than or equal to a predetermined arbitrary field intensity. If the power is less than the predetermined arbitrary field intensity, the switch unit is turned OFF and various commands demodulated by the command demodulation circuit are not inputted to the command decode unit. As a result, the semiconductor integrated circuit device does not operate.
摘要翻译：在IC标签中，当半导体集成电路器件被激活时，操作控制单元设置存在/不存在通信距离限制，以减少与状态管理单元的通信距离。如果没有设定通信距离限制，则开关单元被接通，并且解调命令从命令解调电路输入到命令解码单元。如果设置了通信距离限制，则功率强度监视单元判断整流电路的功率是否大于或等于预定的任意场强。如果功率小于预定的任意场强，则切换单元关闭，并且由命令解调电路解调的各种命令不被输入到命令解码单元。结果，半导体集成电路器件不工作。

3. 发明授权

US08928400B2 Semiconductor device having first and second demodulation circuits for wireless communication 有权
标题翻译：具有用于无线通信的第一和第二解调电路的半导体器件
公开(公告)号：US08928400B2
公开(公告)日：2015-01-06
申请号：US13298897
申请日：2011-11-17
申请人： Takayuki Tsukamoto
发明人： Takayuki Tsukamoto
IPC分类号： H03D1/00 , H04L27/06 , H04B5/00
CPC分类号： H04L27/06 , G06K7/0008 , H03D1/00 , H04B5/0031
摘要： A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.
摘要翻译：当NFC功能半导体器件以除R / W模式之外的模式工作时，器件通过使用与用于R / W模式的ASK信号接收电路不同的ASK信号接收电路来接收ASK信号。在一对发送端子的一侧设置有用于100％ASK的ASK信号接收电路。这种布置消除了在与一对接收终端耦合的10％ASK的ASK信号接收电路内提供的ESD的影响。不需要根据ASK的类型来管理不同的阈值，并且可以通过较小的电路配置来支持不同的调制方案。

4. 发明授权

US08675388B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08675388B2
公开(公告)日：2014-03-18
申请号：US13233679
申请日：2011-09-15
申请人： Yoichi Minemura , Takayuki Tsukamoto , Takafumi Shimotori , Hiroshi Kanno , Natsuki Kikuchi , Mitsuru Sato
发明人： Yoichi Minemura , Takayuki Tsukamoto , Takafumi Shimotori , Hiroshi Kanno , Natsuki Kikuchi , Mitsuru Sato
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C29/025 , G11C29/028 , G11C2013/0083 , G11C2213/71
摘要： A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.
摘要翻译：非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

5. 发明授权

US08410540B2 Non-volatile memory device including a stacked structure and voltage application portion 有权
标题翻译：包括堆叠结构和电压施加部分的非易失性存储器件
公开(公告)号：US08410540B2
公开(公告)日：2013-04-02
申请号：US12886079
申请日：2010-09-20
申请人： Takeshi Araki , Takeshi Yamaguchi , Mariko Hayashi , Kohichi Kubo , Takayuki Tsukamoto
发明人： Takeshi Araki , Takeshi Yamaguchi , Mariko Hayashi , Kohichi Kubo , Takayuki Tsukamoto
IPC分类号： H01L29/792
CPC分类号： G11B9/1472 , B82Y10/00 , G11B5/746 , G11B9/04 , G11B9/149 , G11C13/0007 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/101 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： According to one embodiment, a non-volatile memory device includes a stacked structure including a memory portion and an electrode having a surface facing the memory portion; and a voltage application portion to apply a voltage to the memory portion to change resistance. The surface includes first and second regions. The first region contains a first nonmetallic element and at least one element of a metallic element, Si, Ga, and As. The second region contains a second nonmetallic element and the at least one element. The second region has a content ratio of the second nonmetallic element higher than that in the first region. A difference in electronegativity between the second nonmetallic element and the at least one element is greater than that between the first nonmetallic element and the at least one element. At least one of the first and second regions has an anisotropic shape.
摘要翻译：根据一个实施例，非易失性存储器件包括堆叠结构，其包括存储器部分和具有面向存储器部分的表面的电极; 以及电压施加部分，用于向存储器部分施加电压以改变电阻。表面包括第一和第二区域。第一区域包含第一非金属元素和金属元素Si，Ga和As的至少一种元素。第二区域包含第二非金属元素和至少一个元素。第二区域的第二非金属元素的含量比率高于第一区域。第二非金属元素与至少一种元素之间的电负性的差异大于第一非金属元素与至少一种元素之间的电负性。第一和第二区域中的至少一个具有各向异性形状。

6. 发明授权

US08374571B2 Semiconductor integrated circuit and operating method thereof 有权
标题翻译：半导体集成电路及其操作方法
公开(公告)号：US08374571B2
公开(公告)日：2013-02-12
申请号：US13279408
申请日：2011-10-24
申请人： Atsushi Motozawa , Takayuki Tsukamoto , Tatsuji Matsuura , Yuichi Okuda
发明人： Atsushi Motozawa , Takayuki Tsukamoto , Tatsuji Matsuura , Yuichi Okuda
IPC分类号： H04B1/28 , H04B1/06
CPC分类号： H04B1/40 , H03H11/26 , H03K5/133
摘要： An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.
摘要翻译：集成电路配备有接收混频器和信号发生器。多级延迟电路响应于接收载波信号而产生多个时钟脉冲。相位检测单元检测特定时钟脉冲的电压电平和在特定时钟脉冲之前产生的预定数量的时钟脉冲的电压电平之间的差异，从而检测特定时钟脉冲的预定相位。时钟生成单元的选择器从时钟脉冲信号输出分别具有多个相位的多个选择时钟脉冲信号。第一信号合成逻辑电路对选择时钟脉冲执行逻辑运算，从而产生提供给接收混频器的本地信号。

7. 发明授权

US08305797B2 Information recording/reproducing device 有权
标题翻译：信息记录/再现装置
公开(公告)号：US08305797B2
公开(公告)日：2012-11-06
申请号：US13044384
申请日：2011-03-09
申请人： Shinya Aoki , Kohichi Kubo , Takayuki Tsukamoto , Takahiro Hirai , Chikayoshi Kamata , Tsukasa Nakai
发明人： Shinya Aoki , Kohichi Kubo , Takayuki Tsukamoto , Takahiro Hirai , Chikayoshi Kamata , Tsukasa Nakai
IPC分类号： G11C11/00
CPC分类号： H01L45/1233 , G11B9/04 , G11C13/0011 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/146
摘要： According to one embodiment, an information recording/reproducing device includes a recording layer and a driver section. The recording layer has a first layer including a first compound. The first compound includes a mixed crystal of a first oxide containing a first metallic element and a second oxide. The second oxide has a crystal structure being same as the first oxide and contains a second metallic element different from the first metallic element. The driver section is configured to produce state change in the recording layer to record information by at least one of application of voltage to the recording layer and passage of current to the recording layer. Composition ratio of an element having a smaller ionic radius of the first and second metallic elements is not less than percolation threshold of a lattice formed of ions of the first and second metallic elements based on the crystal structure.
摘要翻译：根据一个实施例，信息记录/再现装置包括记录层和驱动器部分。记录层具有包含第一化合物的第一层。第一化合物包括含有第一金属元素和第二氧化物的第一氧化物的混合晶体。第二氧化物具有与第一氧化物相同的晶体结构，并且含有与第一金属元素不同的第二金属元素。驱动器部分被配置为在记录层中产生状态变化，以通过施加电压至记录层和将电流流向记录层中的至少一个来记录信息。基于晶体结构，第一和第二金属元素离子半径较小的元素的组成比不小于由第一和第二金属元素的离子形成的晶格的渗透阈值。

8. 发明授权

US08288748B2 Information recording and reproducing device 有权
标题翻译：信息记录和再现装置
公开(公告)号：US08288748B2
公开(公告)日：2012-10-16
申请号：US12889558
申请日：2010-09-24
申请人： Takayuki Tsukamoto , Chikayoshi Kamata , Takeshi Yamaguchi , Takahiro Hirai , Shinya Aoki , Kohichi Kubo
发明人： Takayuki Tsukamoto , Chikayoshi Kamata , Takeshi Yamaguchi , Takahiro Hirai , Shinya Aoki , Kohichi Kubo
IPC分类号： H01L29/02
CPC分类号： G11C13/0009 , G11C13/00 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： According to one embodiment, an information recording and reproducing device includes a first layer, a second layer, and a recording layer between the first and second layers, which is capable of a transition between a first state of a low resistance and a second state of a high resistance by flowing a current between the first and second layers. A peripheral portion of the recording layer has a composition different from that of a center portion of the recording layer. The center portion includes two kinds of cation elements. And the center portion is different from the peripheral portion in a ratio of the two kinds of cation elements.
摘要翻译：根据一个实施例，信息记录和再现装置包括第一层和第二层之间的第一层，第二层和记录层，其能够在低电阻的第一状态和第二层之间的转变通过在第一和第二层之间流动电流而产生高电阻。记录层的周边部分具有与记录层的中心部分不同的组成。中心部分包括两种阳离子元件。并且中心部分以两种阳离子元素的比例与周边部分不同。

9. 发明授权

US08237145B2 Nonvolatile memory device with recording layer having two portions of different nitrogen amounts 有权
标题翻译：具有记录层的非易失性存储器件具有两个不同氮量的部分
公开(公告)号：US08237145B2
公开(公告)日：2012-08-07
申请号：US12858975
申请日：2010-08-18
申请人： Chikayoshi Kamata , Takayuki Tsukamoto , Kohichi Kubo , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
发明人： Chikayoshi Kamata , Takayuki Tsukamoto , Kohichi Kubo , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
IPC分类号： H01L29/04 , H01L23/58
CPC分类号： H01L45/06 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1675 , Y10S257/92 , Y10S977/712 , Y10S977/734
摘要： According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion.
摘要翻译：根据一个实施例，非易失性存储器件包括包括第一层，第二层和记录层的层叠体。记录层设置在第一层和第二层之间。记录层能够通过经由第一层和第二层提供的电流在具有高于第一状态的电阻的电阻的第一状态和第二状态之间可逆地改变。记录层包括设置在记录层的主表面的平面中的第一部分和第二部分。第二部分具有比第一部分中的氮量高的氮量。

10. 发明授权

US08014189B2 Information recording/reproducing device 有权
标题翻译：信息记录/再现装置
公开(公告)号：US08014189B2
公开(公告)日：2011-09-06
申请号：US12636554
申请日：2009-12-11
申请人： Takayuki Tsukamoto , Kohichi Kubo , Chikayoshi Kamata , Takahiro Hirai , Shinya Aoki , Toshiro Hiraoka
发明人： Takayuki Tsukamoto , Kohichi Kubo , Chikayoshi Kamata , Takahiro Hirai , Shinya Aoki , Toshiro Hiraoka
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11B9/04 , G11B9/1436 , G11B9/1481 , G11B9/149 , G11C13/0004 , G11C13/0007 , G11C2213/17 , G11C2213/31 , G11C2213/32 , G11C2213/51 , G11C2213/56 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/147 , H01L45/1625
摘要： An information recording/reproducing device includes a recording layer, and a recording circuit which records data to the recording layer by generating a phase change in the recording layer. The recording layer includes a first chemical compound having a spinel structure. The recording layer is AxMyX4 (0.1≦x≦2.2, 1.0≦y≦2.0), where A includes one selected from a group of Zn, Cd and Hg, M includes one selected from a group of Cr, Mo, W, Mn and Re, and X includes O.
摘要翻译：一种信息记录/再现装置，包括记录层，以及通过在记录层中产生相位变化而将数据记录到记录层的记录电路。记录层包括具有尖晶石结构的第一化合物。记录层为AxMyX4（0.1＆nlE; x＆nlE; 2.2,1.0＆nlE; y＆nlE; 2.0），其中A包括选自Zn，Cd和Hg的一种，M包括选自Cr，Mo，W， Mn和Re，X包括O.

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