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1. 发明授权

US5849423A Zinciferous plated steel sheet and method for manufacturing same 失效
标题翻译：镀锌钢板及其制造方法
公开(公告)号：US5849423A
公开(公告)日：1998-12-15
申请号：US751679
申请日：1996-11-18
申请人： Takayuki Urakawa , Toru Imokawa , Michitaka Sakurai , Jun-ichi Inagaki , Masaaki Yamashita , Shuji Nomura
发明人： Takayuki Urakawa , Toru Imokawa , Michitaka Sakurai , Jun-ichi Inagaki , Masaaki Yamashita , Shuji Nomura
IPC分类号： C23C28/00 , C25D5/10 , C25D5/48 , C25D9/04 , B32B3/10 , B32B15/18 , C25D3/56 , C25D5/34
CPC分类号： C25D9/04 , C23C28/3225 , C23C28/345 , C25D5/10 , C25D5/48 , Y10S428/935 , Y10T428/12486 , Y10T428/1266 , Y10T428/12799 , Y10T428/12993
摘要： A method for manufacturing a zinciferous plated steel sheet, comprises: forming a zinciferous plating layer on a steel sheet; and forming an Fe--Ni--O film on the zinciferous plating layer. The Fe--Ni--O film is formed by carrying out electrolysis with the steel sheet as a cathode in an aqueous solution, dipping the steel sheet in an aqueous solution, or spraying a mist on a surface of the zinciferous plating layer.
摘要翻译：一种镀锌钢板的制造方法，其特征在于，在钢板上形成镀锌层; 在镀锌层上形成Fe-Ni-O系膜。 Fe-Ni-O膜是通过在水溶液中用钢板作为阴极进行电解，将钢板浸渍在水溶液中，或者在镀锌层的表面上喷雾而形成的。

2. 发明授权

US06699592B2 Galvannealed steel sheet and method for manufacturing the same 有权
标题翻译：加热冷却钢板及其制造方法
公开(公告)号：US06699592B2
公开(公告)日：2004-03-02
申请号：US10274808
申请日：2002-10-21
申请人： Shoichiro Taira , Yoshiharu Sugimoto , Junichi Inagaki , Toru Imokawa , Shuji Nomura , Michitaka Sakurai , Masaaki Yamashita , Kaoru Sato , Masayasu Nagoshi , Akira Gamou , Yoichi Miyakawa , Shunsaku Node , Masahiro Iwabuchi
发明人： Shoichiro Taira , Yoshiharu Sugimoto , Junichi Inagaki , Toru Imokawa , Shuji Nomura , Michitaka Sakurai , Masaaki Yamashita , Kaoru Sato , Masayasu Nagoshi , Akira Gamou , Yoichi Miyakawa , Shunsaku Node , Masahiro Iwabuchi
IPC分类号： B32B1518
CPC分类号： C23C2/26 , C21D1/673 , C23C2/28 , C23C22/53 , Y10S428/926 , Y10T428/12583 , Y10T428/1259 , Y10T428/12611 , Y10T428/12618 , Y10T428/12799 , Y10T428/12993
摘要： The invention provides a galvannealed steel sheet which has an oxide layer having 10 nm or larger thickness on the plateau of the coating layer flattened by temper rolling. With the use of the galvannealed steel sheet, no powdering occurs during press-forming, and stable and excellent sliding performance is attained. By selecting the area percentage of the plateau of the flattened coating layer to a range from 20 to 80%, making the coating layer single layer of &dgr;1 phase, and letting &zgr; phase exist in the &dgr;1 phase, further improved sliding performance and anti-powdering property are obtained.
摘要翻译：本发明提供一种合金化热浸镀锌钢板，其在通过调质轧制平整的涂层的平台上具有10nm以上的厚度的氧化物层。通过使用合金化热镀锌钢板，在成形时不会发生粉化，可获得稳定且优异的滑动性能。通过选择平整涂层的平台的面积百分比在20〜80％的范围内，使得涂层单层为δ1相，并使ζ相存在于δ1相中，进一步提高滑动性能和抗粉化获得财产。

3. 发明授权

US06723664B2 Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 有权
标题翻译：用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件
公开(公告)号：US06723664B2
公开(公告)日：2004-04-20
申请号：US10041609
申请日：2002-01-10
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： H01L2131
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面密度为10 12 eV -1 cm -2以下，这是通过上述预处理在绝缘体中产生的薄膜沉积工艺。

4. 发明授权

US5767011A Fabrication method for integrated circuits 失效
标题翻译：集成电路制造方法
公开(公告)号：US5767011A
公开(公告)日：1998-06-16
申请号：US749081
申请日：1996-11-14
申请人： Chingchi Yao , Ichiro Yamamoto , Shuji Nomura
发明人： Chingchi Yao , Ichiro Yamamoto , Shuji Nomura
IPC分类号： G06F17/50 , H01L23/528 , H01L21/28
CPC分类号： H01L23/5286 , G06F17/5077 , H01L2924/0002 , Y10S257/923
摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
摘要翻译：一种用于通过集成电路制造互连的方法和结果。该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。所得到的结构还在高电流流动的区域附近提供更多的金属化。类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。还提供了改进的路由技术。这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

5. 发明授权

US08900426B2 Double-layer shutter sputtering apparatus 有权
标题翻译：双层快门溅射装置
公开(公告)号：US08900426B2
公开(公告)日：2014-12-02
申请号：US13316927
申请日：2011-12-12
申请人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/54 , C23C14/34
CPC分类号： C23C14/3464
摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
摘要翻译：一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及通过共溅射至少两个靶，在衬底上形成膜。

6. 发明授权

US06349669B1 Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 失效
标题翻译：用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件
公开(公告)号：US06349669B1
公开(公告)日：2002-02-26
申请号：US09102665
申请日：1998-06-23
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： C23C1600
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。而且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV-1cm-2或更低，这是通过上述绝缘膜沉积工艺中的预处理而得到的。

7. 发明授权

US5923089A Efficient routing method and resulting structure for integrated circuits 失效
标题翻译：集成电路的高效路由方法和结果
公开(公告)号：US5923089A
公开(公告)日：1999-07-13
申请号：US816005
申请日：1997-03-10
申请人： Chingchi Yao , Ichiro Yamamoto , Shuji Nomura
发明人： Chingchi Yao , Ichiro Yamamoto , Shuji Nomura
IPC分类号： G06F17/50 , H01L23/528 , H01L23/48
CPC分类号： H01L23/5286 , G06F17/5077 , H01L2924/0002 , Y10S257/923
摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
摘要翻译：一种用于通过集成电路制造互连的方法和结果。该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。所得到的结构还在高电流流动的区域附近提供更多的金属化。类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。还提供了改进的路由技术。这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

8. 发明授权

US07704556B2 Silicon nitride film forming method 有权
标题翻译：氮化硅膜形成方法
公开(公告)号：US07704556B2
公开(公告)日：2010-04-27
申请号：US11764745
申请日：2007-06-18
申请人： Hitoshi Morisaki , Yasushi Kamiya , Shuji Nomura , Masahiro Totuka , Tomoki Oku , Ryo Hattori
发明人： Hitoshi Morisaki , Yasushi Kamiya , Shuji Nomura , Masahiro Totuka , Tomoki Oku , Ryo Hattori
IPC分类号： C23C16/34
CPC分类号： C23C16/4411 , C23C16/345 , C23C16/44
摘要： The silicon nitride film forming method deposits a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system.
摘要翻译：氮化硅膜形成方法通过将加热元件保持在预定温度并且通过分解和/或激活从气体供应系统供应的原料气体而将氮化硅膜沉积在基板表面上。

9. 发明申请

US20050199490A1 Double-layer shutter control method of multi-sputtering system 有权
标题翻译：多层快门控制方法多溅射系统
公开(公告)号：US20050199490A1
公开(公告)日：2005-09-15
申请号：US11078549
申请日：2005-03-14
申请人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/34 , C23C14/32 , C23C14/54 , C23C14/56
CPC分类号： C23C14/3464
摘要： A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.
摘要翻译：一种在单个室中设置有三个靶的多溅射系统的双层快门控制方法和具有独立旋转并且在其中形成有孔的快门板的双层旋转快门机构，包括通过孔的组合来选择目标的第一快门板和第二快门板，并且使用所选择的靶进行预溅射步骤和主溅射步骤，以连续放电，以便在基板上沉积膜，从而可以防止靶之间的交叉污染由于沉积在快门板上的目标物质等。

10. 发明授权

US6069094A Method for depositing a thin film 失效
标题翻译：沉积薄膜的方法
公开(公告)号：US6069094A
公开(公告)日：2000-05-30
申请号：US924304
申请日：1997-09-05
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： H01L21/205 , C23C16/02 , C23C16/44 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/318
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV -1cm-2或更小，这是通过上述绝缘膜沉积工艺中的预处理所带来的。

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