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1. 发明授权

US08508975B2 Resistive storage-based semiconductor memory device 有权
标题翻译：电阻式存储半导体存储器件
公开(公告)号：US08508975B2
公开(公告)日：2013-08-13
申请号：US12821585
申请日：2010-06-23
申请人： Takayuki Toba , Hiroyuki Nitta
发明人： Takayuki Toba , Hiroyuki Nitta
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C8/14 , G11C13/0007 , G11C13/004 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.
摘要翻译：半导体存储器件包括控制电路。控制电路将第一电压施加到上部互连中的所选择的一个中，将第二电压施加到未选择的上部互连中的一个，将第三电压施加到第一虚拟上部互连并独立地控制要设置的第一至第三电压到不同的值。

2. 发明申请

US20110069524A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110069524A1
公开(公告)日：2011-03-24
申请号：US12821585
申请日：2010-06-23
申请人： Takayuki TOBA , Hiroyuki Nitta
发明人： Takayuki TOBA , Hiroyuki Nitta
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C8/14 , G11C13/0007 , G11C13/004 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.
摘要翻译：半导体存储器件包括控制电路。控制电路将第一电压施加到上部互连中的所选择的一个中，将第二电压施加到未选择的上部互连中的一个，将第三电压施加到第一虚拟上部互连并独立地控制要设置的第一至第三电压到不同的值。

3. 发明授权

US08154560B2 Display drive circuit 有权
标题翻译：显示驱动电路
公开(公告)号：US08154560B2
公开(公告)日：2012-04-10
申请号：US12468345
申请日：2009-05-19
申请人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
发明人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
IPC分类号： G09G5/00 , G09G5/02 , H04N1/46 , H04N1/60 , G06T1/00 , G06K9/00 , G06K9/40
CPC分类号： G09G1/002 , G09G3/3655 , G09G5/04 , G09G5/06 , G09G2320/0242 , G09G2340/145
摘要： A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.
摘要翻译：本发明的显示驱动电路具有：能够存储初始色域顶点坐标的初始色域 - 顶点坐标存储单元; 能够存储用户目标色域顶点坐标的用户对象色彩 - 顶点坐标存储单元; 饱和扩张系数决定单元，用于基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数; 以及用于基于饱和度膨胀系数扩大显示数据的饱和度的扩展单元。基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数，根据扩展系数扩展显示数据的饱和度。因此，可以对于每个色域或LC显示面板的R，G和B颜色属性中的每一个来控制饱和度的扩大程度。

4. 发明授权

US08008704B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08008704B2
公开(公告)日：2011-08-30
申请号：US12372505
申请日：2009-02-17
申请人： Hiroyuki Nitta
发明人： Hiroyuki Nitta
IPC分类号： H01L21/00
CPC分类号： H01L27/11524 , H01L21/764 , H01L23/5222 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.
摘要翻译：为了减小半导体存储器件中每个相邻两个字线之间的电容，在每个相邻的两个存储晶体管的栅极之间的间隙中形成第一绝缘膜，其间具有第一栅极绝缘膜，并且在栅极的选择晶体管和与其相邻的存储晶体管的栅极。此外，第二绝缘膜形成在第一绝缘膜上，每个存储晶体管的栅极的侧面和面向存储晶体管的选择性晶体管的栅极的一侧。第三绝缘膜平行于半导体衬底形成以覆盖金属硅化物膜，第一和第二绝缘膜以及第四和第五绝缘膜。在存储晶体管的每个相邻的两个栅极之间的间隙中以及与选择晶体管的栅极和与其相邻的存储晶体管的栅极之间的空隙中设置空隙部分。每个空隙部分的底部和两侧被第二绝缘膜屏蔽，并且每个空隙部分的顶部被第三绝缘膜屏蔽。

5. 再颁专利

USRE42597E1 Liquid crystal driver and liquid crystal display device using the same 有权
标题翻译：液晶驱动器和液晶显示装置使用相同
公开(公告)号：USRE42597E1
公开(公告)日：2011-08-09
申请号：US11980691
申请日：2007-10-31
申请人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
发明人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3614 , G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0297 , G09G2330/023
摘要： A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.
摘要翻译：液晶驱动器包括：基于参考电压产生灰度电压的电压发生器;以及用于根据显示数据从产生的灰度级电压中选择一个灰度级电压的输出装置，用于施加反相/非反相控制基于所选择的灰度级电压，AC开关信号和反转参考电压相对于反转参考电压的所选择的灰度级电压，并且将用于一个和相同显示数据的不同液晶电源电压输出到液晶面板。

6. 发明申请

US20110038194A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110038194A1
公开(公告)日：2011-02-17
申请号：US12855151
申请日：2010-08-12
申请人： Takeshi MURATA , Yutaka Ishibashi , Hiroyuki Nitta
发明人： Takeshi MURATA , Yutaka Ishibashi , Hiroyuki Nitta
IPC分类号： G11C5/06 , G11C11/00
CPC分类号： G11C5/063 , G11C11/22 , G11C13/0007 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.
摘要翻译：根据一个实施例，半导体存储装置包括在第一方向上延伸的多个平行的第一互连件，多个平行的第二互连件，其沿与第一方向垂直的第二方向延伸，并且相对于所述第一互连和存储单元结构设置在所述第一互连和所述第二互连构成两级交叉的区域中，所述存储单元结构的一端连接到所述第一互连并在另一端连接到所述第二互连，存储单元结构包括串联连接的可变电阻元件和非欧姆元件，其中最末端的第一互连件在至少一部分中断开。

7. 发明授权

US07883964B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07883964B2
公开(公告)日：2011-02-08
申请号：US12181978
申请日：2008-07-29
申请人： Akira Goda , Hiroyuki Nitta
发明人： Akira Goda , Hiroyuki Nitta
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , G11C16/0416 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526
摘要： A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.
摘要翻译：非易失性半导体存储器包括：器件区域和器件隔离区域，其具有沿第一方向延伸的条纹形式的图案，并且在垂直于第一方向的第二方向上以第一间距交替地并且顺序地设置方向; 以及由第一导电材料制成的接触件，其连接到器件区域并沿第二方向以第一间距设置。在第二方向的横截面上，触点的底部宽度比触点的顶部宽度长，并且底部宽度比器件区域的宽度长。

8. 发明授权

US07696959B2 Display device and driving method of the same 有权
标题翻译：显示装置及其驱动方法相同
公开(公告)号：US07696959B2
公开(公告)日：2010-04-13
申请号：US11407043
申请日：2006-04-20
申请人： Hiroyuki Nitta , Masahisa Tsukahara , Toshifumi Ozaki
发明人： Hiroyuki Nitta , Masahisa Tsukahara , Toshifumi Ozaki
IPC分类号： G09G3/22
CPC分类号： G09G3/22 , G09G2310/0267 , G09G2320/0223
摘要： Scan electrode potential detected by a feedback switch is inputted into a negative-phase input terminal of an amplifier, reference selection potential from a reference-selection-potential-signal generation circuit is inputted into a positive-phase input terminal of the amplifier, and the reference-selection-potential-signal generation circuit delays reference potential of a reference voltage source, thereby scan electrode potential without overshooting components can be achieved.
摘要翻译：由反馈开关检测出的扫描电极电位被输入到放大器的负相输入端，参考选择电位信号发生电路的参考选择电位被输入到放大器的正相输入端，参考选择电位信号发生电路延迟参考电压源的参考电位，从而可以实现扫描电极电位，而不会产生过冲成分。

9. 发明授权

US07692618B2 Display device and driving method thereof 失效
标题翻译：显示装置及其驱动方法
公开(公告)号：US07692618B2
公开(公告)日：2010-04-06
申请号：US11657457
申请日：2007-01-25
申请人： Masashi Nakamura , Hiroyuki Nitta , Nobuhiro Takeda , Masahiro Tanaka
发明人： Masashi Nakamura , Hiroyuki Nitta , Nobuhiro Takeda , Masahiro Tanaka
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/30 , G09G2300/08 , G09G2310/062 , G09G2320/0261
摘要： A display device includes a pixel array having a plurality of pixels, a plurality of first signal lines and a plurality of second signal lines. A first driving circuit outputs scanning signals to the plurality of first signal lines, and a second driving circuit outputs display signals to the plurality of second signal lines. Each pixel of the plurality of pixels is operated in a normally black-displaying mode, the first driving circuit repeats a first step of sequentially selecting N lines of the plurality of first signal lines and a second step of selecting Z lines of the plurality of first signal lines that are separate from the N lines, where N and Z are natural numbers, and the second driving circuit repeats outputting N times the display signals and outputting one time a blanking signal which masks an image displayed on corresponding pixels.
摘要翻译：显示装置包括具有多个像素的像素阵列，多个第一信号线和多个第二信号线。第一驱动电路向多条第一信号线输出扫描信号，第二驱动电路向多条第二信号线输出显示信号。多个像素的每个像素以常黑显示模式操作，第一驱动电路重复顺序选择多条第一信号线中的N条线的第一步骤，以及选择多条第一信号线的Z线的第二步骤与N线分离的信号线，其中N和Z是自然数，并且第二驱动电路重复输出N倍的显示信号，并输出一次屏蔽对应像素上显示的图像的消隐信号。

10. 发明申请

US20100052030A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100052030A1
公开(公告)日：2010-03-04
申请号：US12546885
申请日：2009-08-25
申请人： Takeshi SAKAGUCHI , Hiroyuki Nitta
发明人： Takeshi SAKAGUCHI , Hiroyuki Nitta
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L27/11519 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括多个第一有源区，它们沿着第一方向并排设置在存储单元阵列中，并且具有小于通过光刻获得的制造极限尺寸的尺寸，设置在第一方向相邻的第一有源区之间的第二有源区，设置在多个第一有源区中的每一个中并具有存储单元和选择晶体管的存储单元单元，以及连接到第一有源区的一个线性触点存储单元单元的端部并且沿着第一方向延伸，其中设置有线性触点的区域是多个第一有源区域通过多个第二有源区域连接的一个半导体区域，并且底表面的线性接触是平面的。

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