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1. 发明授权

US5670899A Logic circuit controlled by a plurality of clock signals 失效
标题翻译：由多个时钟信号控制的逻辑电路
公开(公告)号：US5670899A
公开(公告)日：1997-09-23
申请号：US556199
申请日：1995-11-09
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： H03K19/003 , H03K19/096 , H03K17/16
CPC分类号： H03K19/0963 , H03K19/00361
摘要： A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control. The CMOS gate is provided with an auxiliary PMOS transistor being inserted at the PMOS transistor side and an auxiliary NMOS transistor being inserted at the NMOS transistor side. A timing control circuit is provided that generates a control clock signal adapted to maintain the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time during which an electric potential output of the CMOS gate varies.
摘要翻译：半导体集成电路具有由时钟信号控制的整体形成的逻辑电路。半导体集成电路包括时钟信号延迟装置，其产生具有相对于参考时钟信号相互偏移少量的相位的多个时钟信号。逻辑电路被分成多个（N个）电路块，使得每个电路块由相关联的多个时钟信号中的每一个控制，以减少噪声。 CMOS集成电路中的噪声也受到受控参考时钟信号的降低。 CMOS集成电路包括至少一个CMOS栅极，其输入端子共同连接到PMOS晶体管和NMOS晶体管的栅极，以及锁存电路，用于通过时钟信号控制将数据发送到CMOS栅极的输入端。 CMOS栅极设置有在PMOS晶体管侧插入的辅助PMOS晶体管，并且在NMOS晶体管侧插入辅助NMOS晶体管。提供了一种定时控制电路，其产生控制时钟信号，该控制时钟信号适于在辅助PMOS晶体管和辅助NMOS晶体管在CMOS栅极的电位输出变化的指定时间段期间保持关断状态。

2. 发明授权

US5021785A Floating point digital to analog converter with bias to establish range midpoint 失效
标题翻译：浮点数字到模拟转换器，偏置建立范围中点
公开(公告)号：US5021785A
公开(公告)日：1991-06-04
申请号：US463876
申请日：1990-01-05
申请人： Takayuki Kohdaka , Katsuhiko Ishida , Toshiyuki Takahashi , Takashi Ogata
发明人： Takayuki Kohdaka , Katsuhiko Ishida , Toshiyuki Takahashi , Takashi Ogata
IPC分类号： H03M1/70 , H03M1/78
CPC分类号： H03M1/70 , H03M1/785
摘要： A digital-to-analog converter converts digital data in the floating-point representation into an analog signal. The mantissa part of the digital data is first converted into a first analog signal by an R-2R resistor ladder network. The first analog signal thus obtained is directly supplied to another r-2r resistor ladder network to produce second analog signals whose values are 2.sup.-N (N=0, 1, 2, . . . ) magnifications of the first analog signal. And, one of the second analog signals is selectively outputted in accordance with the exponent part of the digital data. A data converter is also provided for converting digital data in the form of a fix-point number into floating point data.
摘要翻译：数模转换器将浮点表示中的数字数据转换为模拟信号。数字数据的尾数部分首先通过R-2R电阻梯形网络转换为第一模拟信号。如此获得的第一模拟信号被直接提供给另一个r-2r电阻梯形网络，以产生第二模拟信号，其值为第一模拟信号的2-N（N = 0,1,2 ...）倍率。并且，根据数字数据的指数部分选择性地输出第二模拟信号之一。还提供了一种数据转换器，用于将固定点数形式的数字数据转换为浮点数据。

3. 发明授权

US5245345A Digital-to-analog converter with delta-sigma modulation 失效
标题翻译：具有Δ-Σ调制的数模转换器
公开(公告)号：US5245345A
公开(公告)日：1993-09-14
申请号：US777754
申请日：1991-10-11
申请人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
发明人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
IPC分类号： H03M3/04 , H03H17/00 , H03H17/02 , H03M3/02 , H03M7/00
CPC分类号： H03M3/348 , H03M3/50
摘要： The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.
摘要翻译：数模转换装置与具有短周期的系统时钟信号同步地进行过采样，并对数字输入进行Δ-Σ调制以产生再量化的数字信号。系统时钟信号与由于过采样和Δ-Σ调制操作而被泄漏的噪声混合。系统时钟信号被四分之一或更小的速率分频，以产生具有较长周期并且没有噪声的分频时钟信号。每隔长时间检测重新量化的数字信号，并根据检测结果进行脉冲调制，生成长周期的脉冲信号。该脉冲信号被低通滤波以产生具有改善的S / N比的模拟输出。

4. 发明授权

US6046607A Logic circuit controlled by a plurality of clock signals 失效
标题翻译：由多个时钟信号控制的逻辑电路
公开(公告)号：US6046607A
公开(公告)日：2000-04-04
申请号：US911106
申请日：1997-08-13
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： H03K19/003 , H03K17/16 , H03K19/096
CPC分类号： H03K19/00361 , G06F1/06 , G06F1/10
摘要： A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control. The CMOS gate is provided with an auxiliary PMOS transistor being inserted at the PMOS transistor side and an auxiliary NMOS transistor being inserted at the NMOS transistor side. A timing control circuit is provided that generates a control clock signal adapted to maintain the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time during which an electric potential output of the CMOS gate varies.
摘要翻译：半导体集成电路具有由时钟信号控制的整体形成的逻辑电路。半导体集成电路包括时钟信号延迟装置，其产生具有相对于参考时钟信号相互偏移少量的相位的多个时钟信号。逻辑电路被分成多个（N个）电路块，使得每个电路块由相关联的多个时钟信号中的每一个控制，以减少噪声。 CMOS集成电路中的噪声也受到受控参考时钟信号的降低。 CMOS集成电路包括至少一个CMOS栅极，其输入端子共同连接到PMOS晶体管和NMOS晶体管的栅极，以及锁存电路，用于通过时钟信号控制将数据发送到CMOS栅极的输入端。 CMOS栅极设置有在PMOS晶体管侧插入的辅助PMOS晶体管，并且在NMOS晶体管侧插入辅助NMOS晶体管。提供了一种定时控制电路，其产生控制时钟信号，该控制时钟信号适于在辅助PMOS晶体管和辅助NMOS晶体管在CMOS栅极的电位输出变化的指定时间段期间保持关断状态。

5. 发明授权

US5329172A Chopping type comparator with clocked inverter 失效
标题翻译：带时钟转换器的斩波型比较器
公开(公告)号：US5329172A
公开(公告)日：1994-07-12
申请号：US972588
申请日：1992-11-06
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： G01R19/165 , H03K5/08 , H03K5/24 , H03M1/34
CPC分类号： H03K5/249
摘要： The chopping type comparator is provided with a capacitor which receives at its one end two input signals to be compared with each other through first and second analog switches alternately switchable between a conductive state and a nonconductive state. A clocked inverter is connected at its input terminal to another end of the capacitor. The clocked inverter is changed to an inactive state when one of the first and second analog switches is made conductive. A third analog switch is coupled between the input and output terminals of the clocked inverter. The third analog switch is made conductive concurrently when said one of the first and second analog switches is made conductive.
摘要翻译：斩波型比较器设置有电容器，其在其一端接收两个输入信号，以通过可在导通状态和非导通状态之间交替切换的第一和第二模拟开关彼此进行比较。时钟反相器在其输入端子连接到电容器的另一端。当第一和第二模拟开关之一导通时，时钟反相器变为无效状态。第三个模拟开关耦合在时钟反相器的输入和输出端之间。当所述第一和第二模拟开关之一导通时，第三模拟开关同时导通。

6. 发明授权

US4990917A Parallel analog-to-digital converter 失效
标题翻译：并行模数转换器
公开(公告)号：US4990917A
公开(公告)日：1991-02-05
申请号：US319621
申请日：1989-03-07
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： H03M1/36 , H03M1/00
CPC分类号： H03M1/367
摘要： A parallel analog-to-digital converter having reference-voltage generating means dividing the fundamental reference voltage into exponential reference voltages according to an exponential scale, and further dividing each voltage between two consecutive exponential reference voltages into a plurality of individual reference voltages. As a result, the individual reference voltages have a nonlinear (exponential) characteristic that as the amplitude of an analog input voltage increases, the increment of the individual reference voltages becomes larger exponentially, thus greatly reducing the number of comparators.

7. 发明授权

US5977896A Digital-to-analog converter with delta-sigma modulation 失效
标题翻译：具有Δ-Σ调制的数模转换器
公开(公告)号：US5977896A
公开(公告)日：1999-11-02
申请号：US24000
申请日：1998-02-13
申请人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatsuya Kishii , Kuniaki Morita , Juhro Hoshi
发明人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatsuya Kishii , Kuniaki Morita , Juhro Hoshi
IPC分类号： H03M3/02
CPC分类号： H03M3/51
摘要： The digital-to-analog conversion apparatus operates to convert an digital input into a corresponding analog output. A digital filter is provided for oversampling the digital input having a varying value represented in the form of multiple bits. A delta-sigma modulator operates to effect delta-sigma modulation of the oversampled digital input to reduce a number of the multiple bits for requantizing the oversampled digital input with a certain S/N ratio. A low-pass filter is provided for converting the requantized digital input into an analog output. A level detecting circuit is provided for detecting when the value of the digital input falls below a predetermined level. A shifting circuit is disposed upstream of the delta-sigma modulator and is responsive to the detected results for increasing the value of the digital input so as to improve the S/N ratio in the delta-sigma modulator. An attenuator is disposed downstream of the delta-sigma modulator and is responsive to the detected results for effecting decreasing compensation for the increased value of the digital input while substantially maintaining the improved S/N ratio so as to produce an analog output corresponding to the digital input.
摘要翻译：数模转换装置用于将数字输入转换为对应的模拟输出。提供数字滤波器用于对具有以多位形式表示的变化值的数字输入进行过采样。 Δ-Σ调制器操作以实现过采样数字输入的Δ-Σ调制，以减少用于以某一S / N比重新量化过采样数字输入的多个比特数。提供了一个低通滤波器，用于将再量化的数字输入转换为模拟输出。提供电平检测电路，用于检测数字输入的值何时下降到预定电平以下。移位电路设置在Δ-Σ调制器的上游，并且响应于检测结果以增加数字输入的值，以便提高Δ-Σ调制器中的S / N比。衰减器设置在Δ-Σ调制器的下游，并且响应于检测结果，以便在基本上保持改善的S / N比的同时对增加的数字输入值进行减小的补偿，从而产生对应于数字信号的模拟输出输入。

8. 发明授权

US5570091A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US5570091A
公开(公告)日：1996-10-29
申请号：US310283
申请日：1994-09-21
申请人： Masao Noro , Takayuki Kohdaka
发明人： Masao Noro , Takayuki Kohdaka
IPC分类号： H03M1/06 , H03M1/46 , H03M1/38 , H03M1/12
CPC分类号： H03M1/0692 , H03M1/46
摘要： An analog-to-digital converter mainly comprises an analog-to-digital conversion unit which produces a digital output, as an equivalent of an analog input supplied thereto, by performing a successive approximation. Herein, an instantaneous value of the analog input is compared with a reference signal so as to determine the digit in each of the bits of the digital output. The analog-to-digital converter can further comprise an analog comparator, an analog amplifier and a digital attenuator in order to reduce an effect of the noise. The analog amplifier amplifies the analog input by a gain so as to produce an intermediate analog signal. The analog-to-digital conversion unit converts the intermediate analog signal into an intermediate digital signal. The digital attenuator attenuates the intermediate digital signal by an attenuation rate so as to produce the digital output. The attenuation rate is determined such that a product, obtained by multiplying the gain and attenuation rate together, is normally equal to a value `1`. The analog comparator evaluates the level of the analog input by comparing it with predetermined levels in turn. Thus, the analog comparator controls the gain of the analog amplifier in accordance with a result of the evaluation.
摘要翻译：模数转换器主要包括一个模数转换单元，通过执行逐次逼近，产生一个数字输出，作为提供给它的模拟输入的等价物。这里，将模拟输入的瞬时值与参考信号进行比较，以便确定数字输出的每个比特中的数字。模数转换器还可以包括模拟比较器，模拟放大器和数字衰减器，以便减少噪声的影响。模拟放大器通过增益放大模拟输入，以产生中间模拟信号。模数转换单元将中间模拟信号转换为中间数字信号。数字衰减器通过衰减速率衰减中间数字信号，从而产生数字输出。衰减率被确定为使得通过将增益和衰减率相乘而获得的乘积通常等于值“1”。模拟比较器通过将模拟输入与预定电平进行比较来评估模拟输入的电平。因此，模拟比较器根据评估结果来控制模拟放大器的增益。

9. 发明授权

US5153454A Chopper type comparator 失效
标题翻译：斩波式比较器
公开(公告)号：US5153454A
公开(公告)日：1992-10-06
申请号：US652289
申请日：1991-02-07
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： H03K5/24
CPC分类号： H03K5/249
摘要： A chopper type comparator, for comparing a first analog input signal voltage and a second analog input signal voltage to each other, includes an input portion for inputting the first and second analog input signals, respectively, and selectively outputting the first and second analog input signals, and a comparison portion for providing a result of comparison of the first and second analog input signals. The comparison portion includes a capacitor connected to a selected output of the input means at one terminal of the capacitor, an inverter having an MOS FET and of which an input side thereof connected to the other terminal of the capacitor, a path connected in parallel between the input and an output of the inverter across a analog switch, a switch control portion for controlling an electrical connection state of the analog switch in response to selection of the output of the input portion, the analog switch having a suppressing portion for suppressing transmission of a voltage variation to the input side of the inverter from the output side thereof across the analog switch.
摘要翻译：用于将第一模拟输入信号电压和第二模拟输入信号电压相互比较的斩波器类型比较器包括分别用于输入第一和第二模拟输入信号的输入部分，并且选择性地输出第一和第二模拟输入信号以及用于提供第一和第二模拟输入信号的比较结果的比较部分。比较部分包括连接到电容器的一个端子处的输入装置的选定输出的电容器，具有MOS FET的反相器，其输入侧连接到电容器的另一个端子，逆变器横跨模拟开关的输入和输出，用于响应于输入部分的输出的选择来控制模拟开关的电连接状态的开关控制部分，模拟开关具有抑制部分，用于抑制从模拟开关的输出侧向逆变器的输入侧的电压变化。

10. 发明授权

US4951054A Floating-point digital-to-analog converting system 失效
标题翻译：浮点数模转换系统
公开(公告)号：US4951054A
公开(公告)日：1990-08-21
申请号：US311059
申请日：1989-02-16
申请人： Takayuki Kohdaka
发明人： Takayuki Kohdaka
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/68 , H03M1/785
摘要： A floating-point digital-to-analog converting system which includes a mantissa digital-to-analog converter (DAC) and an exponent DAC. Normally, the mantissa DAC has a digital-to-analog converting accuracy higher than that of the exponent DAC because of differences in their construction. Hence, as long as the accuracy of the mantissa DAC is greater than that of the exponent DAC, an analog mantissa output from the mantissa DAC is used as an analog output of the present system. On other other hand, once the accuracy of the mantissa DAC goes below that of the exponent DAC, data obtained by shifting digital input data is applied to the mantissa DAC. Then, the exponent DAC multiplies the analog mantissa by a weight corresponding to the digital exponent data included in the digital input data. Thus, an analog output is obtained from the exponent DAC.

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