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1. 发明授权

US5245345A Digital-to-analog converter with delta-sigma modulation 失效
标题翻译：具有Δ-Σ调制的数模转换器
公开(公告)号：US5245345A
公开(公告)日：1993-09-14
申请号：US777754
申请日：1991-10-11
申请人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
发明人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
IPC分类号： H03M3/04 , H03H17/00 , H03H17/02 , H03M3/02 , H03M7/00
CPC分类号： H03M3/348 , H03M3/50
摘要： The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.
摘要翻译：数模转换装置与具有短周期的系统时钟信号同步地进行过采样，并对数字输入进行Δ-Σ调制以产生再量化的数字信号。系统时钟信号与由于过采样和Δ-Σ调制操作而被泄漏的噪声混合。系统时钟信号被四分之一或更小的速率分频，以产生具有较长周期并且没有噪声的分频时钟信号。每隔长时间检测重新量化的数字信号，并根据检测结果进行脉冲调制，生成长周期的脉冲信号。该脉冲信号被低通滤波以产生具有改善的S / N比的模拟输出。

2. 发明授权

US5977896A Digital-to-analog converter with delta-sigma modulation 失效
标题翻译：具有Δ-Σ调制的数模转换器
公开(公告)号：US5977896A
公开(公告)日：1999-11-02
申请号：US24000
申请日：1998-02-13
申请人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatsuya Kishii , Kuniaki Morita , Juhro Hoshi
发明人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatsuya Kishii , Kuniaki Morita , Juhro Hoshi
IPC分类号： H03M3/02
CPC分类号： H03M3/51
摘要： The digital-to-analog conversion apparatus operates to convert an digital input into a corresponding analog output. A digital filter is provided for oversampling the digital input having a varying value represented in the form of multiple bits. A delta-sigma modulator operates to effect delta-sigma modulation of the oversampled digital input to reduce a number of the multiple bits for requantizing the oversampled digital input with a certain S/N ratio. A low-pass filter is provided for converting the requantized digital input into an analog output. A level detecting circuit is provided for detecting when the value of the digital input falls below a predetermined level. A shifting circuit is disposed upstream of the delta-sigma modulator and is responsive to the detected results for increasing the value of the digital input so as to improve the S/N ratio in the delta-sigma modulator. An attenuator is disposed downstream of the delta-sigma modulator and is responsive to the detected results for effecting decreasing compensation for the increased value of the digital input while substantially maintaining the improved S/N ratio so as to produce an analog output corresponding to the digital input.
摘要翻译：数模转换装置用于将数字输入转换为对应的模拟输出。提供数字滤波器用于对具有以多位形式表示的变化值的数字输入进行过采样。 Δ-Σ调制器操作以实现过采样数字输入的Δ-Σ调制，以减少用于以某一S / N比重新量化过采样数字输入的多个比特数。提供了一个低通滤波器，用于将再量化的数字输入转换为模拟输出。提供电平检测电路，用于检测数字输入的值何时下降到预定电平以下。移位电路设置在Δ-Σ调制器的上游，并且响应于检测结果以增加数字输入的值，以便提高Δ-Σ调制器中的S / N比。衰减器设置在Δ-Σ调制器的下游，并且响应于检测结果，以便在基本上保持改善的S / N比的同时对增加的数字输入值进行减小的补偿，从而产生对应于数字信号的模拟输出输入。

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