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1. 发明授权

US5694358A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5694358A
公开(公告)日：1997-12-02
申请号：US706267
申请日：1996-09-24
申请人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
发明人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C7/18 , G11C16/06 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/18
摘要： This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.
摘要翻译：本发明提供一种具有字线，与字线交叉的多个位线以及包括MOS晶体管的多个存储单元的非易失性半导体存储器件。 MOS晶体管的每个控制栅极耦合到字线，并且其每个漏极分别耦合到位线。每个MOS晶体管也具有浮动栅极。此外，非易失性半导体存储器件包括锁存电路，第一开关，共同耦合到多个位线的读出放大器和第二开关。锁存电路通过分别耦合在多个位线和锁存电路之间的第一开关耦合到多个位线。第二开关分别耦合在多个位线和读出放大器之间，从而将读出放大器耦合到位线。多个第一开关中的每一个包括MOS晶体管，其源极 - 漏极路径分别位于多个位线中的相应一个位线和相应的一个锁存电路之间。当要从多个存储单元中选择的存储单元读取数据时，多个第一开关被截止，并且所选存储单元和读出放大器之间的第二开关中的一个导通。

2. 发明授权

US06396736B1 Nonvolatile semiconductor memory device which stores multi-value information 有权
标题翻译：存储多值信息的非易失性半导体存储器件
公开(公告)号：US06396736B1
公开(公告)日：2002-05-28
申请号：US09715106
申请日：2000-11-20
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C1604
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

3. 发明授权

US06181603B2 Nonvolatile semiconductor memory device having plural memory cells which store multi-value information 有权
标题翻译：具有存储多值信息的多个存储单元的非易失性半导体存储器件
公开(公告)号：US06181603B2
公开(公告)日：2001-01-30
申请号：US09339960
申请日：1999-06-25
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C1606
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

4. 发明申请

US20070070702A1 Nonvolatile semiconductor memory device which stores multi-value information 失效
公开(公告)号：US20070070702A1
公开(公告)日：2007-03-29
申请号：US11595880
申请日：2006-11-13
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C11/34
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

5. 发明授权

US07031187B2 Nonvolatile semiconductor memory device which stores multi-value information 失效
公开(公告)号：US07031187B2
公开(公告)日：2006-04-18
申请号：US10832311
申请日：2004-04-27
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C16/04
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

6. 发明授权

US07245532B2 Nonvolatile semiconductor memory device which stores multi-value information 失效
标题翻译：存储多值信息的非易失性半导体存储器件
公开(公告)号：US07245532B2
公开(公告)日：2007-07-17
申请号：US11332206
申请日：2006-01-17
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C10/00
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

7. 发明授权

US5982667A Nonvolatile semiconductor memory device for storing multivalue information by controlling erase and plural write states of each memory cell 失效
标题翻译：非易失性半导体存储器件，用于通过控制每个存储器单元的擦除和多个写入状态来存储多值信息
公开(公告)号：US5982667A
公开(公告)日：1999-11-09
申请号：US96457
申请日：1998-06-11
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/06
CPC分类号： G11C11/005 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C7/1006
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

8. 发明授权

US5892713A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5892713A
公开(公告)日：1999-04-06
申请号：US604748
申请日：1996-02-23
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/26 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/04
CPC分类号： G11C7/1042 , G11C16/26
摘要： The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines BL11a-BL14a connected to a word line WL1a in the memory array MAa of the bank A is temporarily stored in the sense & latch circuits SL11-SL14. The information of bit lines is latched to the sense & latch circuit SLa through the sub-input/output signal lines IO1a and IO2a by the switches YS1a and YS2a that alternately operates at a cycle two times that of the external clock. The latched information is then output onto the input/output signal line IOa by the switch SWa in synchronism with the clock. After the four bit lines BL11a-SB14a have been read out, the sense & latch circuits SL11-S114 in that block are reset and the bit lines on the bank B are precharged while the information on the bank A is being output. After the reading on the bank A is finished, the word line on the bank B is raised to a high level to execute the read operation in the similar manner. In this way, the word lines on the two banks are alternately raised to the high level for continuous and alternate reading. This configuration provides a nonvolatile semiconductor memory device which allows high-speed block reading.
摘要翻译：存储垫被分成两个组，它们共享感测和锁存电路。作为电路操作的示例，包含在与存储体A的存储器阵列MAa中的字线WL1a连接的四个位线BL11a-BL14a的块中的存储单元中的信息被临时存储在感测和锁存电路SL11中 -SL14。开关YS1a，YS2a通过子输入输出信号线IO1a，IO2a将位线的信息锁存在感测和锁存电路SLa上，开关YS1a，YS2a以外部时钟的2倍的周期进行交替动作。然后锁存的信息由开关SWa与时钟同步地输出到输入/输出信号线IOa。在四位位线BL11a-SB14a被读出之后，该块中的读出和锁存电路SL11-S114被复位，并且在输出有关存储体A上的信息时，对存储体B上的位线进行预充电。在银行A的读取结束后，银行B上的字线升高到高水平，以类似的方式执行读取操作。以这种方式，两行的字线交替地升高到高电平以进行连续和交替读取。该配置提供了允许高速块读取的非易失性半导体存储器件。

9. 发明授权

US5870218A Nonvolatile semiconductor memory device which stores multi-value information 失效
公开(公告)号：US5870218A
公开(公告)日：1999-02-09
申请号：US841612
申请日：1997-04-30
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C11/34
CPC分类号： G11C11/005 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C7/1006
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

10. 发明申请

US20090016102A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTI-VALUE INFORMATION 审中-公开
标题翻译：存储多值信息的非易失性半导体存储器件
公开(公告)号：US20090016102A1
公开(公告)日：2009-01-15
申请号：US12117918
申请日：2008-05-09
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

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