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1. 发明申请

US20050001255A1 MIM capacitor having flat diffusion prevention films 失效
公开(公告)号：US20050001255A1
公开(公告)日：2005-01-06
申请号：US10902579
申请日：2004-07-30
申请人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
发明人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06 , H01L27/08 , H01L27/108
CPC分类号： H01L28/60 , H01L27/0629 , H01L27/0805
摘要： At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.

2. 发明授权

US07045415B2 MIM capacitor having flat diffusion prevention films 失效
标题翻译：具有平坦扩散防止膜的MIM电容器
公开(公告)号：US07045415B2
公开(公告)日：2006-05-16
申请号：US10902579
申请日：2004-07-30
申请人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
发明人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L27/0629 , H01L27/0805
摘要： At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.
摘要翻译：目前，Cu（铜）被用作布线材料。在作为RF模拟装置和CMOS逻辑装置的组合的RF-CMOS装置中，MIM电容器的两个电极由具有大扩散系数的Cu形成。为了防止Cu向MIM电容器的电容器绝缘膜扩散，具有防止扩散的功能的扩散防止膜插入在电容器绝缘膜和两个电极之间。结果，形成电极的Cu不扩散到电容器绝缘膜。

3. 发明授权

US06894331B2 MIM capacitor having flat diffusion prevention films 失效
标题翻译：具有平坦扩散防止膜的MIM电容器
公开(公告)号：US06894331B2
公开(公告)日：2005-05-17
申请号：US09734658
申请日：2000-12-13
申请人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
发明人： Takashi Yoshitomi , Tatsuya Ohguro , Ryoji Hasumi , Hideki Kimijima , Takashi Yamaguchi , Masahiro Inohara
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06 , H01L27/08 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/60 , H01L27/0629 , H01L27/0805
摘要： At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.
摘要翻译：目前，Cu（铜）被用作布线材料。在作为RF模拟装置和CMOS逻辑装置的组合的RF-CMOS装置中，MIM电容器的两个电极由具有大扩散系数的Cu形成。为了防止Cu向MIM电容器的电容器绝缘膜扩散，具有防止扩散的功能的扩散防止膜插入电容器绝缘膜和两个电极之间。结果，形成电极的Cu不扩散到电容器绝缘膜。

4. 发明申请

US20050224898A1 MOSFET with a thin gate insulating film 失效
标题翻译：具有薄栅绝缘膜的MOSFET
公开(公告)号：US20050224898A1
公开(公告)日：2005-10-13
申请号：US11143594
申请日：2005-06-03
申请人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
发明人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
IPC分类号： H01L21/225 , H01L21/336 , H01L27/088 , H01L29/423 , H01L29/76 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/2256 , H01L21/28211 , H01L27/0629 , H01L27/088 , H01L29/42364 , H01L29/42372 , H01L29/78
摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
摘要翻译：半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成所述基板的栅电极（2）以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅电极（2）和漏区（6）的电压为1.5V以下。因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

5. 发明授权

US06642560B2 MOSFET with a thin gate insulating film 失效
标题翻译：具有薄栅绝缘膜的MOSFET
公开(公告)号：US06642560B2
公开(公告)日：2003-11-04
申请号：US10160036
申请日：2002-06-04
申请人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
发明人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
IPC分类号： H01L2976
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/2256 , H01L21/28211 , H01L27/0629 , H01L27/088 , H01L29/42364 , H01L29/42372 , H01L29/78
摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
摘要翻译：半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成在所述基体上的栅电极（2）以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。特别地，绝缘膜（3）的厚度（Tox）在氧化硅膜的转换率（氧化硅当量厚度））被确定为小于2.5nm。栅电极（2）的栅极长度（Lg）被确定为等于或小于0.3μm; 并且进一步施加到栅极（2）和漏极区（6）的电压被确定为1.3V或更小。因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

6. 发明授权

US06229164B1 MOSFET with a thin gate insulating film 失效
标题翻译：具有薄栅绝缘膜的MOSFET
公开(公告)号：US06229164B1
公开(公告)日：2001-05-08
申请号：US09440938
申请日：1999-11-16
申请人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
发明人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
IPC分类号： H01L2976
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/2256 , H01L21/28211 , H01L27/0629 , H01L27/088 , H01L29/42364 , H01L29/42372 , H01L29/78
摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
摘要翻译：半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成在所述基板上的栅电极（2）以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。特别地，绝缘膜（3）的厚度（TOX）在氧化硅膜的转换率（氧化硅当量厚度））被确定为小于2.5nm。电极（2）的栅极长度（Lg）被确定为等于或小于0.3μm; 并且进一步施加到栅极（2）和漏极区（6）的电压被确定为1.5V或更小。因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

7. 发明授权

US5955761A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5955761A
公开(公告)日：1999-09-21
申请号：US69980
申请日：1998-04-30
申请人： Takashi Yoshitomi , Hiroshi Iwai , Masanobu Saito , Hisayo Momose , Tatsuya Ohguro , Mizuki Ono
发明人： Takashi Yoshitomi , Hiroshi Iwai , Masanobu Saito , Hisayo Momose , Tatsuya Ohguro , Mizuki Ono
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/45 , H01L29/78 , H01L27/088
CPC分类号： H01L29/66628 , H01L21/2652 , H01L21/823864 , H01L27/0928 , H01L29/0847 , H01L29/456 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.
摘要翻译：能够抑制短通道效应并获得尽可能高的电流驱动性的半导体器件包括半导体衬底，形成在该衬底的表面上的栅极绝缘膜，形成在该栅极绝缘膜上的栅电极和侧壁在该栅电极上形成的绝缘膜和栅极绝缘膜的侧壁。半导体器件还包括与侧壁绝缘膜相邻形成的侧壁导体膜和形成在侧壁导电膜下的基板的表面区域中的源极/漏极区域以及与侧壁导电膜相邻的表面区域的半导体衬底。在侧壁导体膜的表面作为起始点的基板的深度方向上的杂质浓度在预定深度呈现一个最大值，但在比预定深度更深的部分中减小。

8. 发明授权

US5736767A Semiconductor device including a CMOSFET of a single-gate 失效
标题翻译：包括具有单栅极结构的CMOSFET的半导体器件
公开(公告)号：US5736767A
公开(公告)日：1998-04-07
申请号：US675720
申请日：1996-07-02
申请人： Takashi Yoshitomi , Tatsuya Ohguro
发明人： Takashi Yoshitomi , Tatsuya Ohguro
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928 , H01L29/7833 , H01L29/7838
摘要： A semiconductor device including a CMOSFET having first and second channel type MOSFETs, respectively formed in a first semiconductor region of a first conductivity type and in a second semiconductor region of a second conductivity type. The first channel type MOSFET has a first gate electrode insulatively formed on the first region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, first source/drain regions of the second conductivity type respectively formed in the first region and having a LDD structure, and a buried channel region of the second conductivity type formed just below the first gate electrode. The second channel type MOSFET has a second gate electrode insulatively formed on the second region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, second source/drain regions of the first conductivity type respectively formed in the second region and having a LDD structure.
摘要翻译：一种半导体器件，包括具有第一和第二沟道型MOSFET的CMOSFET，分别形成在第一导电类型的第一半导体区域和第二导电类型的第二半导体区域中。第一沟道型MOSFET具有第一栅极电极，绝缘地形成在第一区域上，由第一导电型半导体制成，栅极长度为0.2μm以下，第二导电类型的第一源极/漏极区分别形成在所述第一区域具有LDD结构，以及形成在所述第一栅电极正下方的所述第二导电类型的掩埋沟道区。第二沟道型MOSFET具有在第二区域上隔绝地形成的第二栅电极，由第一导电型半导体制成，栅极长度为0.2μm以下，第一导电类型的第二源/漏区分别形成在第二区域并具有LDD结构。

9. 发明授权

US07282752B2 MOSFET with a thin gate insulating film 失效
标题翻译：具有薄栅绝缘膜的MOSFET
公开(公告)号：US07282752B2
公开(公告)日：2007-10-16
申请号：US11143594
申请日：2005-06-03
申请人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
发明人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
IPC分类号： H01L29/76
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/2256 , H01L21/28211 , H01L27/0629 , H01L27/088 , H01L29/42364 , H01L29/42372 , H01L29/78
摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
摘要翻译：半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成所述基板的栅电极（2）以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅电极（2）和漏区（6）的电压为1.5V以下。因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

10. 发明授权

US5990516A MOSFET with a thin gate insulating film 失效
标题翻译：具有薄栅绝缘膜的MOSFET
公开(公告)号：US5990516A
公开(公告)日：1999-11-23
申请号：US527562
申请日：1995-09-13
申请人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
发明人： Hisayo Momose , Hiroshi Iwai , Masanobu Saito , Tatsuya Ohguro , Mizuki Ono , Takashi Yoshitomi , Shinichi Nakamura
IPC分类号： H01L21/225 , H01L21/336 , H01L27/088 , H01L29/423 , H01L29/76 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/2256 , H01L21/28211 , H01L27/0629 , H01L27/088 , H01L29/42364 , H01L29/42372 , H01L29/78
摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (T.sub.OX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (L.sub.g) of the gate electrode (2) is determined to be equal to or less than 0.3 .mu.m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
摘要翻译：半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成在所述基板上的栅电极（2）以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。特别地，绝缘膜（3）的厚度（TOX）在氧化硅膜的转换率（氧化硅当量厚度））被确定为小于2.5nm。栅电极（2）的栅极长度（Lg）被确定为等于或小于0.3μm; 并且进一步施加到栅极（2）和漏极区（6）的电压被确定为1.5V或更小。因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

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