专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5161228A System with selectively exclusionary enablement for plural indirect address type interrupt control circuit 失效
标题翻译：具有多个间接地址类型中断控制电路的选择性排除启用的系统
公开(公告)号：US5161228A
公开(公告)日：1992-11-03
申请号：US317808
申请日：1989-03-02
申请人： Takashi Yasui , Masanobu Fukushima , Kazuhiko Hara
发明人： Takashi Yasui , Masanobu Fukushima , Kazuhiko Hara
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： An indirect address type interrupt control circuit is provided. A plurality of interrupt control units are provided for receiving an input interrupt signal and generating a vector address which corresponds to the interrupt signal. Also provided in the circuit is a control unit which responds to the input interrupt signal to cause only one of the plurality of interrupt control units which corresponds to the interrupt signal to be rendered operative. With this structure, the number of interrupt request signals can be increased or decreased with ease.
摘要翻译：提供间接地址型中断控制电路。提供多个中断控制单元用于接收输入中断信号并产生对应于中断信号的向量地址。电路中还设置有响应于输入中断信号的控制单元，使得仅与中断信号对应的多个中断控制单元中的一个能够被执行。利用这种结构，可以容易地增加或减少中断请求信号的数量。

2. 发明授权

US4922441A Gate array device having a memory cell/interconnection region 失效
标题翻译：具有存储单元/互连区域的门阵列器件
公开(公告)号：US4922441A
公开(公告)日：1990-05-01
申请号：US143715
申请日：1988-01-14
申请人： Toshihiro Tsukagoshi , Masanobu Fukushima , Keiichi Yoshioka , Takashi Yasui
发明人： Toshihiro Tsukagoshi , Masanobu Fukushima , Keiichi Yoshioka , Takashi Yasui
IPC分类号： G11C11/412 , G11C17/12 , H01L27/11 , H01L27/118 , H03K19/173 , G06F15/60
CPC分类号： H01L27/1104 , G11C11/412 , G11C17/12 , H01L27/11 , H01L27/1108 , H01L27/118 , H03K19/1735
摘要： A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
摘要翻译：门阵列器件包括彼此间隔开的多个基本单元区域，从而在其间限定多个中间区域。每个中间区域可以至少部分地用作存储器或功能单元区域或者作为互连区域。可以通过金属化将存储单元区域选择性地定义为ROM或RAM。可以根据控制信号选择性地设置测试模式或正常操作模式。当正常操作模式被设置时，输入端通过逻辑电路可操作地连接到存储器电路; 而当设置测试模式时，输入端直接连接到存储器电路，同时旁路逻辑电路。还提供了一种存储单元结构，其可以被定义为RAM存储器单元或者通过金属化存储选择的二进制数据的ROM存储单元。

3. 发明授权

US5696957A Integrated circuit comprising a central processing unit for executing a plurality of programs 失效
标题翻译：集成电路，包括用于执行多个节目的中央处理单元
公开(公告)号：US5696957A
公开(公告)日：1997-12-09
申请号：US593482
申请日：1996-01-29
申请人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
发明人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/3012 , G06F9/462
摘要： An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.
摘要翻译：集成电路具有用于执行程序的中央处理单元。集成电路包括设置在中央处理单元中的寄存器组，用于存储在中央处理单元中执行程序所需的箱; 以及耦合到中央处理单元的寄存器文件RAM，用于存储至少与存储在中央处理单元中的寄存器中的数据相同的数据，其中存储在寄存器文件RAM中的数据可以被提供给寄存器组在中央处理单位。

4. 发明授权

US08442939B2 File sharing method, computer system, and job scheduler 有权
标题翻译：文件共享方法，计算机系统和作业调度程序
公开(公告)号：US08442939B2
公开(公告)日：2013-05-14
申请号：US12388174
申请日：2009-02-18
申请人： Takashi Yasui , Masaaki Shimizu
发明人： Takashi Yasui , Masaaki Shimizu
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30168 , G06F2221/2147
摘要： Provided is a computer system including a plurality of computing hosts, which constructs a shared file system dynamically so that job execution efficiency is improved. In the computer system which includes the plurality of computing hosts and executes a job requested, in a case where the job is executed by the plurality of computing hosts, each computing host which executes the job is configured to: share a file necessary for executing the job; access the shared file to execute the requested job; and cancel the sharing of the file after execution of the requested job is completed.
摘要翻译：提供了一种包括多个计算主机的计算机系统，其动态地构建共享文件系统，从而提高作业执行效率。在包括多个计算主机并执行所请求的作业的计算机系统中，在由多个计算主机执行作业的情况下，执行该作业的每个计算主机被配置为：共享执行所需的文件工作; 访问共享文件以执行请求的作业; 并在完成所请求的作业的执行后取消共享文件。

5. 发明申请

US20070287077A1 Photomask and exposure method 有权
标题翻译：光掩模和曝光方法
公开(公告)号：US20070287077A1
公开(公告)日：2007-12-13
申请号：US11802005
申请日：2007-05-18
申请人： Katsuhiro Takushima , Takashi Yasui
发明人： Katsuhiro Takushima , Takashi Yasui
IPC分类号： A47G1/12 , G03F1/14 , G03F1/00
CPC分类号： G03F1/64 , G03F1/62
摘要： To provide a photomask capable of preventing a foreign matter generation in using the photomask, and an exposure method using this photomask. The photomask includes a transparent substrate 2; a transfer pattern 4 formed in a main region 3 of a center portion of the transparent substrate 2; a light-shading band region 5 provided adjacent to the main region 3 in the outer peripheral region of the main region 3; and a pellicle 6 formed by adhering a pellicle film 6a to a pellicle frame 6b by an adhesive 8a, wherein this pellicle 6 is adhered onto a light-shading region 7 consisting of a light-shading film formed in the outer peripheral region of the main region 3, through an adhesive 8b.
摘要翻译：提供能够防止在使用光掩模中产生异物的光掩模和使用该光掩模的曝光方法。光掩模包括透明基板2; 形成在透明基板2的中心部分的主区域3中的转印图案4; 在主区域3的外周区域中与主区域3相邻设置的遮光带区域5; 以及通过粘合剂8a将防护薄膜6a粘附在防护薄膜组件6b上形成的防护薄膜组件6，其中该防护薄膜组件6粘附在由形成在外围区域中的遮光膜构成的遮光区域7上的主区域3，通过粘合剂8b。

6. 发明授权

US5511173A Programmable logic array and data processing unit using the same 失效
标题翻译：可编程逻辑阵列和数据处理单元使用相同
公开(公告)号：US5511173A
公开(公告)日：1996-04-23
申请号：US177794
申请日：1994-01-05
申请人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
发明人： Shinichi Yamaura , Takashi Yasui , Keiichi Yoshioka
IPC分类号： G06F9/32 , G06F9/22 , H03K19/177 , G06F9/30
CPC分类号： H03K19/1772 , G06F9/223
摘要： A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.
摘要翻译：可编程逻辑阵列包括多个AND平面。每个AND平面执行AND逻辑运算，并具有输入端和输出端。可编程逻辑阵列还包括为多个AND平面共同提供的单个OR平面。单OR平面执行或逻辑运算，并且具有耦合到多个AND平面和输出端的输出端的输入端。还提供了使用上述可编程逻辑阵列的数据处理单元。

7. 发明授权

US4043801A Method of simultaneously controlling temperature and carbon content of molten steel at the end-point in oxygen top-blown converter 失效
标题翻译：同时控制氧气顶吹转炉终点钢水温度和碳含量的方法
公开(公告)号：US4043801A
公开(公告)日：1977-08-23
申请号：US598756
申请日：1975-07-25
申请人： Eiichi Sakamoto , Masanobu Kubo , Takashi Yasui , Katsuya Suzuki , Katsuhiko Tachibana
发明人： Eiichi Sakamoto , Masanobu Kubo , Takashi Yasui , Katsuya Suzuki , Katsuhiko Tachibana
IPC分类号： C21C5/30
CPC分类号： C21C5/30
摘要： In the refining of steel by an oxygen topblown converter, the temperature and carbon content of molten steel are simultaneously measured by a sensor at a predetermined time before the end point, whereby in accordance with the difference between a calculated carbon content at the endpoint obtained by processing the measured values and a target carbon content at the end-point, the oxygen quantity to be blown in at the end-point and the coolant requirement or the pattern of soft-blow are computed to simultaneously control the temperature and carbon content of the molten steel at the end-point.
摘要翻译：在通过氧气顶吹转化器精炼钢中，在端点之前的预定时间，通过传感器同时测量钢水的温度和碳含量，由此根据由终点获得的计算得到的碳含量之差在终点处理测量值和目标碳含量，计算在终点吹入的氧气量和冷却液要求或软吹模式，以同时控制温度和碳含量钢水终点。

8. 发明授权

US12066508B2 Magnetic field measuring apparatus and magnetic field measuring method 有权
公开(公告)号：US12066508B2
公开(公告)日：2024-08-20
申请号：US17429479
申请日：2020-03-16
申请人： Takashi Yasui
发明人： Takashi Yasui
IPC分类号： G01R33/035 , A61B5/243 , A61B5/245 , A61B5/248 , H03H17/02
CPC分类号： G01R33/0356 , A61B5/243 , A61B5/245 , A61B5/248 , H03H17/02 , A61B2562/0223
摘要： A magnetic field measuring apparatus includes an A/D conversion unit, an integration unit, and a post-processing unit. The A/D conversion unit is configured to sample a signal at a predetermined sampling frequency and perform conversion into digital data, the signal being based on an output voltage from a superconducting quantum interference device configure to detect a magnetic field emanating from a living organism. The integration unit is configured to obtain a biological magnetic field signal based on a value obtained by integrating the digital data, the biological magnetic field signal indicating a magnetic field emanating from the living organism. The post-processing unit is configured to perform decimation processing on the biological magnetic field signal output from the integration unit.

9. 发明授权

US11435416B2 Magnetic field measuring apparatus 有权
公开(公告)号：US11435416B2
公开(公告)日：2022-09-06
申请号：US17077270
申请日：2020-10-22
申请人： Takashi Yasui
发明人： Takashi Yasui
IPC分类号： G01R33/00 , G01R33/035
摘要： A magnetic field measuring apparatus includes a digital FLL circuit. The digital FLL circuit includes a first amplifier configured to amplify voltage output by a superconducting quantum interference device in accordance with strength of a magnetic field strength, an AD converter configured to, convert analog signals to first digital values, an integrator configured to integrate the first digital values output by the AD converter, a DA converter configured to receive an integral value output by the integrator as a second digital value, convert the second digital value to voltage, and output the converted voltage, a signal switcher configured to connect an output of the first amplifier or an output of the DA converter to an input of the AD converter, and a storage unit configured to store a correction value that corrects the integral value received by the DA converter.

10. 发明授权

US08067132B2 Photomask and exposure method 有权
标题翻译：光掩模和曝光方法
公开(公告)号：US08067132B2
公开(公告)日：2011-11-29
申请号：US11802005
申请日：2007-05-18
申请人： Katsuhiro Takushima , Takashi Yasui
发明人： Katsuhiro Takushima , Takashi Yasui
IPC分类号： G03F1/00 , H01L21/00
CPC分类号： G03F1/64 , G03F1/62
摘要： To provide a photomask capable of preventing a foreign matter generation in using the photomask, and an exposure method using this photomask. The photomask includes a transparent substrate 2; a transfer pattern 4 formed in a main region 3 of a center portion of the transparent substrate 2; a light-shading band region 5 provided adjacent to the main region 3 in the outer peripheral region of the main region 3; and a pellicle 6 formed by adhering a pellicle film 6a to a pellicle frame 6b by an adhesive 8a, wherein this pellicle 6 is adhered onto a light-shading region 7 consisting of a light-shading film formed in the outer peripheral region of the main region 3, through an adhesive 8b.
摘要翻译：提供能够防止在使用光掩模中产生异物的光掩模和使用该光掩模的曝光方法。光掩模包括透明基板2; 形成在透明基板2的中心部分的主区域3中的转印图案4; 在主区域3的外周区域中与主区域3相邻设置的遮光带区域5; 以及通过粘合剂8a将防护薄膜6a粘接到防护薄膜框架6b上形成的防护薄膜组件6，其中该防护薄膜组件6粘附到由形成在主体的外围区域中的遮光膜构成的遮光区域7上区域3，通过粘合剂8b。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式