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1. 发明授权

US07522896B2 Filter control method, signal processing circuit and integrated circuit for wireless receiver 失效
标题翻译：无线接收机的滤波器控制方法，信号处理电路和集成电路
公开(公告)号：US07522896B2
公开(公告)日：2009-04-21
申请号：US11251922
申请日：2005-10-18
申请人： Takashi Oshima , Masaru Kokubo
发明人： Takashi Oshima , Masaru Kokubo
IPC分类号： H04B1/06 , H04B1/16
CPC分类号： H04B1/1027
摘要： A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.
摘要翻译：控制滤波器的通带的常规方法涉及由于用于确定干扰波的电平的检测电路的大面积而导致芯片的成本增加。本发明利用通过利用自动增益控制电路检测信号的幅度电平而获得的结果来适当地控制滤波器的通带。通过利用自动增益控制电路检测包括期望波和干扰波的所有信号的振幅电平，从而基于结果控制滤波器的通带。

2. 发明授权

US07138838B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US07138838B2
公开(公告)日：2006-11-21
申请号：US10765129
申请日：2004-01-28
申请人： Yoshiyuki Shibahara , Masaru Kokubo , Takashi Oshima
发明人： Yoshiyuki Shibahara , Masaru Kokubo , Takashi Oshima
IPC分类号： H03L7/06
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/197
摘要： A variable loop bandwidth phase locked loop in which, upon input of a succession of signals “1”, no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.
摘要翻译：一种可变环路带宽锁相环，其中在输入一系列信号“1”时，不发生调制信号劣化，甚至在高符号速率下，参考信号频率保持较低，并且相位频率检测器而Σ-Δ电路保持低电平。锁相环包括：第一调制器，其将基带信号TX_DATA转换成用于指定分割数的整数信号，并将其发送到可编程分频器的控制端; 第二调制器，将输入的基带信号整形为规定的信号波形，并将其发送到压控振荡器; 以及根据控制信号CUR改变锁相环的环路带宽的可变电流电荷泵。

3. 发明申请

US20090096540A1 LOGICAL LEVEL CONVERTER AND PHASE LOCKED LOOP USING THE SAME 审中-公开
标题翻译：使用相同的逻辑电平转换器和相位锁定环路
公开(公告)号：US20090096540A1
公开(公告)日：2009-04-16
申请号：US12243553
申请日：2008-10-01
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
IPC分类号： H03L7/085
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译：逻辑电平转换器产生输出信号，由此即使存在阈值波动因子，逻辑电路也能精确地操作。在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。基于比较结果输出阈值设定信号。阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

4. 发明授权

US07446614B2 Logical level converter and phase locked loop using the same 失效
标题翻译：逻辑电平转换器和锁相环使用相同
公开(公告)号：US07446614B2
公开(公告)日：2008-11-04
申请号：US11403968
申请日：2006-04-14
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
IPC分类号： H03L7/085 , H03L7/089 , H03L7/099
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译：逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。将来自阈值可变逆变器的另一输出信号的直流分量输入到比较器，并与比较电压进行比较。基于比较结果输出阈值设定信号。阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

5. 发明申请

US20060261873A1 Logical level converter and phase locked loop using the same 失效
标题翻译：逻辑电平转换器和锁相环使用相同
公开(公告)号：US20060261873A1
公开(公告)日：2006-11-23
申请号：US11403968
申请日：2006-04-14
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
IPC分类号： H03K12/00
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译：逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。基于比较结果输出阈值设定信号。阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

6. 发明申请

US20060084402A1 Filter control method, signal processing circuit and integrated circuit for wireless receiver 失效
公开(公告)号：US20060084402A1
公开(公告)日：2006-04-20
申请号：US11251922
申请日：2005-10-18
申请人： Takashi Oshima , Masaru Kokubo
发明人： Takashi Oshima , Masaru Kokubo
IPC分类号： H04B1/06 , H04L27/08
CPC分类号： H04B1/1027
摘要： A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.

7. 发明申请

US20120155301A1 Wireless Network System and Wireless Communication Device 有权
标题翻译：无线网络系统和无线通信设备
公开(公告)号：US20120155301A1
公开(公告)日：2012-06-21
申请号：US13308635
申请日：2011-12-01
申请人： Masayuki MIYAZAKI , Kenichi Mizugaki , Masaru Kokubo , Hideyuki Nagaishi , Nobuhisa Kobayashi
发明人： Masayuki MIYAZAKI , Kenichi Mizugaki , Masaru Kokubo , Hideyuki Nagaishi , Nobuhisa Kobayashi
IPC分类号： H04W24/00
CPC分类号： H04W28/06 , H04L1/0002 , H04L1/0014 , H04L43/00 , H04L67/12 , H04L69/04 , H04L2001/0097 , H04W4/38 , H04W24/10 , H04W84/18 , Y02D70/00
摘要： A wireless communication device includes a sensor processing unit that generates sensor data including a measurement result acquired by a sensor; a communication measurement unit that generates communication quality data including a communication state for transmitting a packet; a compression determination unit that determines compression rates of first sensor data and first communication quality data according to the contents of the first sensor data including the transmitted sensor data and the generated sensor data or the contents of the first communication quality data including the transmitted sensor data and the generated communication quality data; a compression unit that compresses the first sensor data and the first communication quality data according to the determined compression rates; and a wireless communication unit that transmits a packet including the compressed first sensor data and the compressed first communication quality data to another wireless communication device or the access point.
摘要翻译：无线通信装置包括传感器处理单元，其生成包括由传感器获取的测量结果的传感器数据; 通信测量单元，其生成包括用于发送分组的通信状态的通信质量数据; 压缩确定单元，其根据包括所发送的传感器数据和所生成的传感器数据的第一传感器数据的内容或包括所发送的传感器数据的第一通信质量数据的内容来确定第一传感器数据和第一通信质量数据的压缩率和生成的通信质量数据; 压缩单元，其根据确定的压缩率压缩第一传感器数据和第一通信质量数据; 以及无线通信单元，其将包括压缩的第一传感器数据和压缩的第一通信质量数据的分组发送到另一无线通信设备或接入点。

8. 发明授权

US08179733B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08179733B2
公开(公告)日：2012-05-15
申请号：US13080958
申请日：2011-04-06
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C7/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

9. 发明授权

US07602665B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07602665B2
公开(公告)日：2009-10-13
申请号：US12169253
申请日：2008-07-08
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C5/14
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

10. 发明授权

US07339489B2 Sensor with wireless communication function 失效
标题翻译：传感器具有无线通讯功能
公开(公告)号：US07339489B2
公开(公告)日：2008-03-04
申请号：US10786542
申请日：2004-02-26
申请人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
发明人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
IPC分类号： G08B23/00
CPC分类号： G08B25/10
摘要： A sensor transmits and receives wireless signals at intervals. A sensor unit, a processor 130, a wireless transmitter circuit, and a wireless receiver circuit are activated in sequence only for a fixed time when the electric power generated by a generator circuit and charged in a capacitor reaches a preset level. Sensing information detected by the sensor unit is processed by the processor circuit and, information on the number of receivable bytes is added to the processing results in the wireless receiver circuit. This added information is sent as sensor information to the wireless host from the wireless transmitting circuit, and the wireless receiver circuit that activated after the wireless transmitter circuit was activated, receives a control information signal from the wireless host. This received information is processed in the processor circuit.
摘要翻译：传感器间隔地发送和接收无线信号。传感器单元，处理器130，无线发射器电路和无线接收器电路仅在发电机产生的电力并在电容器中充电的电力达到预设电平的固定时间内被依次激活。由传感器单元检测到的感测信息由处理器电路处理，并且关于可接收字节数的信息被添加到无线接收器电路中的处理结果。该添加的信息作为传感器信息从无线发送电路发送到无线主机，并且在无线发射机电路被激活之后激活的无线接收机电路从无线主机接收控制信息信号。该接收到的信息在处理器电路中被处理。

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