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1. 发明申请

US20120155301A1 Wireless Network System and Wireless Communication Device 有权
标题翻译：无线网络系统和无线通信设备
公开(公告)号：US20120155301A1
公开(公告)日：2012-06-21
申请号：US13308635
申请日：2011-12-01
申请人： Masayuki MIYAZAKI , Kenichi Mizugaki , Masaru Kokubo , Hideyuki Nagaishi , Nobuhisa Kobayashi
发明人： Masayuki MIYAZAKI , Kenichi Mizugaki , Masaru Kokubo , Hideyuki Nagaishi , Nobuhisa Kobayashi
IPC分类号： H04W24/00
CPC分类号： H04W28/06 , H04L1/0002 , H04L1/0014 , H04L43/00 , H04L67/12 , H04L69/04 , H04L2001/0097 , H04W4/38 , H04W24/10 , H04W84/18 , Y02D70/00
摘要： A wireless communication device includes a sensor processing unit that generates sensor data including a measurement result acquired by a sensor; a communication measurement unit that generates communication quality data including a communication state for transmitting a packet; a compression determination unit that determines compression rates of first sensor data and first communication quality data according to the contents of the first sensor data including the transmitted sensor data and the generated sensor data or the contents of the first communication quality data including the transmitted sensor data and the generated communication quality data; a compression unit that compresses the first sensor data and the first communication quality data according to the determined compression rates; and a wireless communication unit that transmits a packet including the compressed first sensor data and the compressed first communication quality data to another wireless communication device or the access point.
摘要翻译：无线通信装置包括传感器处理单元，其生成包括由传感器获取的测量结果的传感器数据; 通信测量单元，其生成包括用于发送分组的通信状态的通信质量数据; 压缩确定单元，其根据包括所发送的传感器数据和所生成的传感器数据的第一传感器数据的内容或包括所发送的传感器数据的第一通信质量数据的内容来确定第一传感器数据和第一通信质量数据的压缩率和生成的通信质量数据; 压缩单元，其根据确定的压缩率压缩第一传感器数据和第一通信质量数据; 以及无线通信单元，其将包括压缩的第一传感器数据和压缩的第一通信质量数据的分组发送到另一无线通信设备或接入点。

2. 发明授权

US08179733B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08179733B2
公开(公告)日：2012-05-15
申请号：US13080958
申请日：2011-04-06
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C7/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

3. 发明申请

US20100027369A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100027369A1
公开(公告)日：2010-02-04
申请号：US12577365
申请日：2009-10-12
申请人： Yuichi OKUDA , Masaru KOKUBO , Yoshinobu NAKAGOME , Hideharu YAHATA , Hiroki MIYASHITA
发明人： Yuichi OKUDA , Masaru KOKUBO , Yoshinobu NAKAGOME , Hideharu YAHATA , Hiroki MIYASHITA
IPC分类号： G11C8/16
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

4. 发明授权

US07602665B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07602665B2
公开(公告)日：2009-10-13
申请号：US12169253
申请日：2008-07-08
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C5/14
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

5. 发明授权

US07522896B2 Filter control method, signal processing circuit and integrated circuit for wireless receiver 失效
标题翻译：无线接收机的滤波器控制方法，信号处理电路和集成电路
公开(公告)号：US07522896B2
公开(公告)日：2009-04-21
申请号：US11251922
申请日：2005-10-18
申请人： Takashi Oshima , Masaru Kokubo
发明人： Takashi Oshima , Masaru Kokubo
IPC分类号： H04B1/06 , H04B1/16
CPC分类号： H04B1/1027
摘要： A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.
摘要翻译：控制滤波器的通带的常规方法涉及由于用于确定干扰波的电平的检测电路的大面积而导致芯片的成本增加。本发明利用通过利用自动增益控制电路检测信号的幅度电平而获得的结果来适当地控制滤波器的通带。通过利用自动增益控制电路检测包括期望波和干扰波的所有信号的振幅电平，从而基于结果控制滤波器的通带。

6. 发明授权

US07339489B2 Sensor with wireless communication function 失效
标题翻译：传感器具有无线通讯功能
公开(公告)号：US07339489B2
公开(公告)日：2008-03-04
申请号：US10786542
申请日：2004-02-26
申请人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
发明人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
IPC分类号： G08B23/00
CPC分类号： G08B25/10
摘要： A sensor transmits and receives wireless signals at intervals. A sensor unit, a processor 130, a wireless transmitter circuit, and a wireless receiver circuit are activated in sequence only for a fixed time when the electric power generated by a generator circuit and charged in a capacitor reaches a preset level. Sensing information detected by the sensor unit is processed by the processor circuit and, information on the number of receivable bytes is added to the processing results in the wireless receiver circuit. This added information is sent as sensor information to the wireless host from the wireless transmitting circuit, and the wireless receiver circuit that activated after the wireless transmitter circuit was activated, receives a control information signal from the wireless host. This received information is processed in the processor circuit.
摘要翻译：传感器间隔地发送和接收无线信号。传感器单元，处理器130，无线发射器电路和无线接收器电路仅在发电机产生的电力并在电容器中充电的电力达到预设电平的固定时间内被依次激活。由传感器单元检测到的感测信息由处理器电路处理，并且关于可接收字节数的信息被添加到无线接收器电路中的处理结果。该添加的信息作为传感器信息从无线发送电路发送到无线主机，并且在无线发射机电路被激活之后激活的无线接收机电路从无线主机接收控制信息信号。该接收到的信息在处理器电路中被处理。

7. 发明授权

US07031675B2 FM transmitter 失效
公开(公告)号：US07031675B2
公开(公告)日：2006-04-18
申请号：US10067234
申请日：2002-02-07
申请人： Masaru Kokubo
发明人： Masaru Kokubo
IPC分类号： H01Q11/12
CPC分类号： H04B1/04
摘要： An FM transmitter that can control start/idle of each of such devices as a buffer amplifier without using a sample-and-hold circuit for moving a PLL into open loop control, wherein a controller that controls a charging pump in the PLL to start/idle the FM modulation is controlled with use of a closed/open loop select signal of the PLL, a start/idle signal of the buffer amplifier, and a preamble detection signal. The power consumption of the FM transmission can be reduced, since both the buffer amplifier and the PLL in the FM transmitter can be started/idled together in a ganged manner.

8. 发明授权

US06731101B2 Modulation semiconductor integrated circuit device and testing method for oscillation circuit 失效
标题翻译：调制半导体集成电路器件及振荡电路的测试方法
公开(公告)号：US06731101B2
公开(公告)日：2004-05-04
申请号：US10086718
申请日：2002-03-04
申请人： Hirokazu Miyagawa , Katsumi Yamamoto , Tatsuji Matsuura , Masaru Kokubo
发明人： Hirokazu Miyagawa , Katsumi Yamamoto , Tatsuji Matsuura , Masaru Kokubo
IPC分类号： H03H1328
CPC分类号： H04B1/525 , H03B5/1215 , H03B5/1231 , H03B5/1243 , H04B1/52
摘要： In accomplishing an LC-oscillation VCO circuit which is immune to frequency deviation and a frequency-hopping radio communication apparatus using the VCO circuit, a modulation semiconductor integrated circuit device is designed to control the LC-oscillation VCO directly with data to be transmitted thereby implementing the modulation and switch the carrier frequency for frequency hopping. The integrated circuit device includes a current adjusting circuit which varies the current value of a D/A conversion circuit for producing a control voltage of VCO in accordance with the carrier frequency so that the variation of a modulation control voltage of VCO has a characteristic that is opposite to the characteristic of modulation frequency deviation, thereby nullifying the modulation frequency deviation of VCO.
摘要翻译：在实现对频率偏移免疫的LC振荡VCO电路和使用VCO电路的跳频无线电通信装置的情况下，调制半导体集成电路装置被设计成直接用要发送的数据来控制LC振荡VCO，从而实现调制和切换跳频的载波频率。集成电路装置包括电流调节电路，其根据载波频率改变用于产生VCO的控制电压的D / A转换电路的电流值，使得VCO的调制控制电压的变化具有与调制频率偏差的特性相反，从而使VCO的调制频率偏差无效。

9. 发明授权

US06594197B2 Semiconductor integrated circuit device 有权
公开(公告)号：US06594197B2
公开(公告)日：2003-07-15
申请号：US10185044
申请日：2002-07-01
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： H03K300
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

10. 发明授权

US06215364B1 Variable frequency oscillator, and phase locked loop and clock synchronizer using thereof 有权
标题翻译：变频振荡器，以及使用其的锁相环和时钟同步器
公开(公告)号：US06215364B1
公开(公告)日：2001-04-10
申请号：US09288689
申请日：1999-04-09
申请人： Changku Hwang , Masaru Kokubo
发明人： Changku Hwang , Masaru Kokubo
IPC分类号： H03B502
CPC分类号： H03K3/0315 , H03L7/0893 , H03L7/0896 , H03L7/0995 , H03L7/10 , H03L2207/06
摘要： The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof. The positive feedback circuit, provided between output terminals of the differential amplifier, a controlling MOS transistor for inputting a frequency control signal for controlling the source current of the complementary amplifier to the gate thereof and the complementary amplifiers are connected in series between a power supply terminal and a ground terminal.
摘要翻译：变频振荡器能够在低电源电压下工作，并以高频振荡。锁相环和时钟同步器使用可变频率振荡器并具有宽的振荡频率范围。可变频率振荡器具有级联的多个延迟单元，并且最后级延迟单元的输出反馈到第一级延迟单元的输入。每个延迟单元包括差分放大器和正反馈电路，与彼此相交的输入和输出端子连接。反馈电路具有互补放大器，每个互补放大器具有通过将pMOS和nMOS晶体管的栅极连接在一起形成的输入端子和通过将其漏极连接而形成的输出端子。在差分放大器的输出端子之间设置的正反馈电路，用于输入用于控制互补放大器的源电流至其栅极的频率控制信号的控制MOS晶体管和互补放大器串联连接在电源端子和地面终端。

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