专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5188280A Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals 失效
标题翻译：接合金属的方法以及使用所述金属接合方法制造半导体集成电路器件的方法和装置
公开(公告)号：US5188280A
公开(公告)日：1993-02-23
申请号：US812024
申请日：1991-12-23
申请人： Takashi Nakao , Yoshiaki Emoto , Koichiro Sekiguchi , Masayuki Iketani , Kunizo Sahara , Ikuo Yoshida , Akiomi Kohno , Masaya Horino , Hideaki Kamohara , Shouichi Irie , Hiroshi Akasaki , Kanji Otsuka
发明人： Takashi Nakao , Yoshiaki Emoto , Koichiro Sekiguchi , Masayuki Iketani , Kunizo Sahara , Ikuo Yoshida , Akiomi Kohno , Masaya Horino , Hideaki Kamohara , Shouichi Irie , Hiroshi Akasaki , Kanji Otsuka
IPC分类号： H01L21/48 , H01L21/60 , H01L23/055 , H01L23/498 , H05K3/34
CPC分类号： H01L24/81 , H01L21/4853 , H01L23/055 , H01L23/49816 , H05K3/3478 , H01L2224/11003 , H01L2224/13111 , H01L2224/136 , H01L2224/16225 , H01L2224/73253 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H05K2203/0113 , H05K2203/016 , H05K2203/0338 , H05K2203/041 , H05K3/3489
摘要： A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
摘要翻译：具有高可靠性的芯片安装型封装或TAB封装的生产技术，不使用会导致环境污染或阻碍可靠性提高的焊剂，更具体地涉及一种照射焊接面的方法，焊接面以及具有原子或离子能量束的封装的焊料凸块电极，并且在连续设备中在常压（约1atm）下将结合表面彼此粘合。

2. 发明授权

US5090609A Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals 失效
标题翻译：接合金属的方法以及使用所述金属接合方法制造半导体集成电路器件的方法和装置
公开(公告)号：US5090609A
公开(公告)日：1992-02-25
申请号：US514943
申请日：1990-04-26
申请人： Takashi Nakao , Yoshiaki Emoto , Koichiro Sekiguchi , Masayuki Iketani , Kunizo Sahara , Ikuo Yoshida , Akiomi Kohno , Masaya Horino , Hideaki Kamohara , Shouichi Irie , Hiroshi Akasaki , Kanji Otsuka
发明人： Takashi Nakao , Yoshiaki Emoto , Koichiro Sekiguchi , Masayuki Iketani , Kunizo Sahara , Ikuo Yoshida , Akiomi Kohno , Masaya Horino , Hideaki Kamohara , Shouichi Irie , Hiroshi Akasaki , Kanji Otsuka
IPC分类号： H01L21/48 , H01L21/60 , H01L23/055 , H01L23/498 , H05K3/34
CPC分类号： H01L24/81 , H01L21/4853 , H01L23/055 , H01L23/49816 , H05K3/3478 , H01L2224/11003 , H01L2224/11334 , H01L2224/13111 , H01L2224/136 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H05K2203/0113 , H05K2203/016 , H05K2203/0338 , H05K2203/041 , H05K3/3489
摘要： An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
摘要翻译：本发明涉及一种具有高可靠性的芯片安装型封装或TAB封装的生产技术，而不使用会引起环境污染或阻碍可靠性提高的焊剂，更具体地涉及一种照射焊接表面的方法，以及具有原子或离子能量束的封装的焊料凸块电极，并且在连续设备中在常压（约1atm）下将结合表面彼此粘合。

3. 发明授权

US5107329A Pin-grid array semiconductor device 失效
标题翻译：针阵阵列半导体器件
公开(公告)号：US5107329A
公开(公告)日：1992-04-21
申请号：US315608
申请日：1989-02-27
申请人： Takayuki Okinaga , Kanji Otsuka , Hiroshi Akasaki
发明人： Takayuki Okinaga , Kanji Otsuka , Hiroshi Akasaki
IPC分类号： H01L23/50 , H01L23/057 , H01L23/498 , H05K1/18 , H05K3/30 , H05K3/34
CPC分类号： H01L23/49827 , H01L23/057 , H01L23/49811 , H05K3/303 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/181 , H05K2201/10568 , H05K2201/10659 , H05K2201/10704 , H05K2203/167 , H05K3/3426 , H05K3/3447 , Y02P70/613
摘要： A semiconductor device of pin-grid array (PGA) type, which is adapted for surface-mounting on a printed circuit board, has lead pins arranged in a grid and standing perpendicularly on a base of the semiconductor device. In addition, a few pins are provided which are longer than said lead pins in said grid. When the device is placed on the printed circuit board for mounting, the longer pins are inserted into through-holes which are respectively formed in the printed circuit board to correspond to the position of the longer pins of the device. Thus, the tip of the lead pins are accurately positioned on the top of lands on the printed circuit board, respectively, and the lead pins do not get out of position during the mounting operation.
摘要翻译：针对栅极阵列（PGA）类型的半导体器件适用于表面安装在印刷电路板上，具有布置成格栅并垂直于半导体器件的基座垂直放置的引线引脚。此外，提供了比所述电网中的所述引线引脚长的几个引脚。当将装置放置在印刷电路板上用于安装时，较长的针被插入到分别形成在印刷电路板中的通孔中，以对应于装置的较长销的位置。因此，引脚的尖端分别精确地定位在印刷电路板上的焊盘的顶部，并且引线引脚在安装操作期间不会脱离位置。

4. 发明授权

US5217922A Method for forming a silicide layer and barrier layer on a semiconductor device rear surface 失效
标题翻译：在半导体器件后表面上形成硅化物层和阻挡层的方法
公开(公告)号：US5217922A
公开(公告)日：1993-06-08
申请号：US810313
申请日：1991-12-19
申请人： Hiroshi Akasaki , Kanji Otsuka , Tetsuya Hayashida
发明人： Hiroshi Akasaki , Kanji Otsuka , Tetsuya Hayashida
IPC分类号： H01L21/52 , H01L21/50 , H01L21/58 , H01L21/60 , H01L23/12
CPC分类号： H01L24/32 , H01L21/50 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/04026 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/29111 , H01L2224/73253 , H01L2224/81801 , H01L2224/8319 , H01L2224/8385 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , Y10T29/49144 , Y10T29/49149
摘要： A method of manufacturing a semiconductor device wherein the back surface of a semiconductor chip is adhered closely to a substrate or a seal member through a soldering material or the like, and a metallized layer is formed on the back surface of the chip for attaining good adhesion. The metallized layer according to the present invention is a layer formed by laminating a metal silicide, a barrier metal and an oxidation preventing metal successively on the back of the chip. The layer of the metal silicide can be formed in a known heat treatment process, for example, simultaneously with the formation of bump electrodes, on a main surface of the semiconductor chip by the heat used at the time of forming such bump electrodes, or simultaneously with the mounting of the semiconductor chip by the heat used at the time of the chip mounting.
摘要翻译：一种制造半导体器件的方法，其中半导体芯片的背表面通过焊接材料等紧密地粘合到基底或密封构件上，并且在芯片的背面上形成金属化层以获得良好的粘附力。根据本发明的金属化层是通过在芯片的背面依次层叠金属硅化物，阻挡金属和防氧化金属形成的层。金属硅化物层可以在已知的热处理工艺中形成，例如，在形成凸起电极的同时形成凸起电极的同时，通过在形成这种凸起电极时使用的热量在半导体芯片的主表面上形成通过在芯片安装时使用的热量来安装半导体芯片。

5. 发明申请

US20050265091A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050265091A1
公开(公告)日：2005-12-01
申请号：US11137583
申请日：2005-05-26
申请人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
发明人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
IPC分类号： G11C29/04 , G11C11/401 , G11C11/4091 , G11C29/00
CPC分类号： G11C29/84 , G11C11/401 , G11C11/4091
摘要： A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.
摘要翻译：提供一种半导体存储器件，其能够提高驱动字线时的可靠性并且能够减少由于缺陷缓解引起的访问延迟。为了防止冗余存储器存储器的正常存储器字符串和子字线的子字线的多次选择，冗余存储器衬垫的开始被延迟到正常存储器垫的开始，并且按顺序为了补偿起始延迟，消除了共享电路，并且在冗余存储器垫中减少了位线长度。通过这样做，位线的读取时间减少并且信号量增加。因此，读出放大器与正常存储器垫相同的激活定时也可以用在冗余存储器垫中。

6. 发明授权

US06794678B2 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法
公开(公告)号：US06794678B2
公开(公告)日：2004-09-21
申请号：US10058787
申请日：2002-01-30
申请人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
发明人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C11/401 , G11C11/41 , G11C29/14 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
摘要翻译：控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中，内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中，响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

7. 发明授权

US07113434B2 Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle 失效
标题翻译：具有用于产生具有时差的定时信号的可编程延迟的半导体集成电路是时钟周期的非整数倍
公开(公告)号：US07113434B2
公开(公告)日：2006-09-26
申请号：US10823664
申请日：2004-04-14
申请人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
发明人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C2207/104
摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
摘要翻译：在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍的时钟信号。

8. 发明授权

US06570800B2 High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal 失效
标题翻译：高速时钟同步半导体存储器，其中列地址选通信号根据时钟信号而变化
公开(公告)号：US06570800B2
公开(公告)日：2003-05-27
申请号：US09756800
申请日：2001-01-10
申请人： Yousuke Tanaka , Masahiro Katayama , Yuji Yokoyama , Hiroshi Akasaki , Shuichi Miyaoka , Toru Kobayashi
发明人： Yousuke Tanaka , Masahiro Katayama , Yuji Yokoyama , Hiroshi Akasaki , Shuichi Miyaoka , Toru Kobayashi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/18 , G11C11/4096
摘要： The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.
摘要翻译：以时钟信号周期多次的周期改变的列地址选通信号（CAS）被输入到存储块（MBK0〜MBKn）。当列地址信号（CASADR）为“0”时，每个周期输出从存储单元阵列（10）读出并与并行/串行转换器电路（21）并行/串行转换的多个串行数据，改变了并行数据输入到存储器块，并且与时钟信号周期同步地由串行/并行转换器电路（25）串行/并行转换的并行数据被写入存储单元阵列中。以这种方式，列地址选通信号的访问规范每时钟信号的n个周期改变一次，从而允许更快速的存储器操作。

9. 发明申请

US20050018461A1 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法
公开(公告)号：US20050018461A1
公开(公告)日：2005-01-27
申请号：US10918421
申请日：2004-08-16
申请人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
发明人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C29/12 , G11C29/14 , G11C29/48 , G11C29/50 , G11C29/56 , G11C19/08
CPC分类号： G11C29/48 , G11C11/401 , G11C11/41 , G11C29/14 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
摘要翻译：控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中，内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中，响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

10. 发明授权

US07184330B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07184330B2
公开(公告)日：2007-02-27
申请号：US11137583
申请日：2005-05-26
申请人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
发明人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
IPC分类号： G11C29/00
CPC分类号： G11C29/84 , G11C11/401 , G11C11/4091
摘要： A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.
摘要翻译：提供一种半导体存储器件，其能够提高驱动字线时的可靠性并且能够减少由于缺陷缓解引起的访问延迟。为了防止冗余存储器存储器的正常存储器字符串和子字线的子字线的多次选择，冗余存储器衬垫的开始被延迟到正常存储器垫的开始，并且按顺序为了补偿起始延迟，消除了共享电路，并且在冗余存储器垫中减少了位线长度。通过这样做，位线的读取时间减少并且信号量增加。因此，读出放大器与正常存储器垫相同的激活定时也可以用在冗余存储器垫中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式