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1. 发明申请

US20050265091A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050265091A1
公开(公告)日：2005-12-01
申请号：US11137583
申请日：2005-05-26
申请人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
发明人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
IPC分类号： G11C29/04 , G11C11/401 , G11C11/4091 , G11C29/00
CPC分类号： G11C29/84 , G11C11/401 , G11C11/4091
摘要： A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.
摘要翻译：提供一种半导体存储器件，其能够提高驱动字线时的可靠性并且能够减少由于缺陷缓解引起的访问延迟。为了防止冗余存储器存储器的正常存储器字符串和子字线的子字线的多次选择，冗余存储器衬垫的开始被延迟到正常存储器垫的开始，并且按顺序为了补偿起始延迟，消除了共享电路，并且在冗余存储器垫中减少了位线长度。通过这样做，位线的读取时间减少并且信号量增加。因此，读出放大器与正常存储器垫相同的激活定时也可以用在冗余存储器垫中。

2. 发明授权

US07184330B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07184330B2
公开(公告)日：2007-02-27
申请号：US11137583
申请日：2005-05-26
申请人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
发明人： Kenichi Tajima , Hiroshi Akasaki , Masatoshi Hasegawa , Yousuke Tanaka
IPC分类号： G11C29/00
CPC分类号： G11C29/84 , G11C11/401 , G11C11/4091
摘要： A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.
摘要翻译：提供一种半导体存储器件，其能够提高驱动字线时的可靠性并且能够减少由于缺陷缓解引起的访问延迟。为了防止冗余存储器存储器的正常存储器字符串和子字线的子字线的多次选择，冗余存储器衬垫的开始被延迟到正常存储器垫的开始，并且按顺序为了补偿起始延迟，消除了共享电路，并且在冗余存储器垫中减少了位线长度。通过这样做，位线的读取时间减少并且信号量增加。因此，读出放大器与正常存储器垫相同的激活定时也可以用在冗余存储器垫中。

3. 发明申请

US20070159901A1 Semiconductor Integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070159901A1
公开(公告)日：2007-07-12
申请号：US11708348
申请日：2007-02-21
申请人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
发明人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译：提供了其操作加快并且功耗降低的DRAM。提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。

4. 发明授权

US07193912B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07193912B2
公开(公告)日：2007-03-20
申请号：US11136510
申请日：2005-05-25
申请人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
发明人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
IPC分类号： G11C7/00 , G11C7/02 , G11C11/34
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译：提供了其操作加快并且功耗降低的DRAM。提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。

5. 发明申请

US20050265096A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050265096A1
公开(公告)日：2005-12-01
申请号：US11136510
申请日：2005-05-25
申请人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
发明人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
IPC分类号： H01L27/108 , G11C7/00 , G11C7/12 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/105
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译：提供了其操作加快并且功耗降低的DRAM。提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。

6. 发明授权

US07440350B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07440350B2
公开(公告)日：2008-10-21
申请号：US11708348
申请日：2007-02-21
申请人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
发明人： Tadahiro Obara , Masatoshi Hasegawa , Yousuke Tanaka , Tomofumi Hokari , Kenichi Tajima
IPC分类号： G11C7/02 , G11C5/06 , G11C11/50
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译：提供了其操作加快并且功耗降低的DRAM。提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。

7. 发明申请

US20050018461A1 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法
公开(公告)号：US20050018461A1
公开(公告)日：2005-01-27
申请号：US10918421
申请日：2004-08-16
申请人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
发明人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C29/12 , G11C29/14 , G11C29/48 , G11C29/50 , G11C29/56 , G11C19/08
CPC分类号： G11C29/48 , G11C11/401 , G11C11/41 , G11C29/14 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
摘要翻译：控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中，内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中，响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

8. 发明授权

US07113434B2 Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle 失效
标题翻译：具有用于产生具有时差的定时信号的可编程延迟的半导体集成电路是时钟周期的非整数倍
公开(公告)号：US07113434B2
公开(公告)日：2006-09-26
申请号：US10823664
申请日：2004-04-14
申请人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
发明人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C2207/104
摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
摘要翻译：在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍的时钟信号。

9. 发明授权

US06794678B2 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法
公开(公告)号：US06794678B2
公开(公告)日：2004-09-21
申请号：US10058787
申请日：2002-01-30
申请人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
发明人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C11/401 , G11C11/41 , G11C29/14 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
摘要翻译：控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中，内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中，响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

10. 发明授权

US07162671B2 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法
公开(公告)号：US07162671B2
公开(公告)日：2007-01-09
申请号：US10918421
申请日：2004-08-16
申请人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
发明人： Masatoshi Hasegawa , Shuichi Miyaoka , Hiroshi Akasaki , Masahiro Katayama
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C11/401 , G11C11/41 , G11C29/14 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
摘要翻译：控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中，内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中，响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

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