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1. 发明授权

US07968463B2 Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer 有权
标题翻译：金属化合物层的形成方法，半导体装置的制造方法以及金属化合物层的形成装置
公开(公告)号：US07968463B2
公开(公告)日：2011-06-28
申请号：US12227714
申请日：2007-05-21
申请人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
发明人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L29/665
摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.
摘要翻译：金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。半导体器件的制造方法采用这种金属化合物层的形成方法。

2. 发明申请

US20090170252A1 Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer 有权
标题翻译：金属化合物层的形成方法，半导体装置的制造方法以及金属化合物层的形成装置
公开(公告)号：US20090170252A1
公开(公告)日：2009-07-02
申请号：US12227714
申请日：2007-05-21
申请人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
发明人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
IPC分类号： H01L21/8234 , B05C11/00 , H01L21/285
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L29/665
摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.
摘要翻译：金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。半导体器件的制造方法采用这种金属化合物层的形成方法。

3. 发明申请

US20100084713A1 Semiconductor device manufacturing method and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20100084713A1
公开(公告)日：2010-04-08
申请号：US12311428
申请日：2007-09-27
申请人： Takashi Nakagawa , Toru Tatsumi , Kenzo Manabe , Kensuke Takahashi , Makiko Oshida
发明人： Takashi Nakagawa , Toru Tatsumi , Kenzo Manabe , Kensuke Takahashi , Makiko Oshida
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/823842 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A second mask is provided so as to cover a second gate pattern and a first gate pattern is heated to a temperature at which a material gas containing a first metal thermally decomposes, polysilicon constituting the first gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the first gate pattern is turned into a first gate electrode constituted by a silicide of the first metal. After the second mask is removed, a first mask is provided so as to cover the first electrode and the second gate pattern is heated to a temperature at which the material gas thermally decomposes, polysilicon constituting the second gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the second gate pattern is turned into a second gate electrode constituted by the silicide of the first metal. Then, the first mask is removed. With such a manufacturing method, a silicide layer is formed without adding an annealing process.
摘要翻译：提供第二掩模以覆盖第二栅极图案，并且将第一栅极图案加热到含有第一金属的材料气体热分解的温度，构成第一栅极图案的多晶硅与第一金属进行硅化反应第一金属层不沉积的条件，因此第一栅极图案变成由第一金属的硅化物构成的第一栅电极。在去除第二掩模之后，提供第一掩模以覆盖第一电极，并且将第二栅极图案加热到材料气体热分解的温度，构成第二栅极图案的多晶硅与第一金属反应，在第一金属层不沉积的条件下进行硅化，因此第二栅极图案变成由第一金属的硅化物构成的第二栅电极。然后，删除第一个掩模。通过这样的制造方法，不添加退火处理而形成硅化物层。

4. 发明申请

US20070138580A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070138580A1
公开(公告)日：2007-06-21
申请号：US10575785
申请日：2005-06-21
申请人： Kensuke Takahashi , Kenzo Manabe , Nobuyuki Ikarashi , Toru Tatsumi
发明人： Kensuke Takahashi , Kenzo Manabe , Nobuyuki Ikarashi , Toru Tatsumi
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/4975 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high dielectric constant and a metal gate electrode, and significantly enhancing performances without deterioration in reliability of a device. The semiconductor device includes a gate insulating film composed of a material having a high dielectric constant, and a gate electrode. A portion of the gate electrode making contact with the gate insulating film has a composition including silicide of metal M expressed with MxSi1-X (0 0.5) in a p-type MOSFET, and is equal to or smaller than 0.5 (X≦0.5) in a n-type MOSFET.
摘要翻译：提供一种半导体器件，其能够解决CMOS晶体管中的阈值控制的问题，伴随着具有高介电常数的栅极绝缘膜和金属栅极电极的组合，并且显着提高性能而不劣化器件的可靠性。半导体器件包括由具有高介电常数的材料构成的栅极绝缘膜和栅电极。与栅极绝缘膜接触的栅电极的一部分具有以MxSi 1-X（0 0.5），并且在n型MOSFET中等于或小于0.5（X <= 0.5）。

5. 发明授权

US07592674B2 Semiconductor device with silicide-containing gate electrode and method of fabricating the same 有权
标题翻译：具有含硅化物的栅电极的半导体器件及其制造方法
公开(公告)号：US07592674B2
公开(公告)日：2009-09-22
申请号：US10575785
申请日：2005-06-21
申请人： Kensuke Takahashi , Kenzo Manabe , Nobuyuki Ikarashi , Toru Tatsumi
发明人： Kensuke Takahashi , Kenzo Manabe , Nobuyuki Ikarashi , Toru Tatsumi
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/4975 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high dielectric constant and a metal gate electrode, and significantly enhancing performances without deterioration in reliability of a device. The semiconductor device includes a gate insulating film composed of a material having a high dielectric constant, and a gate electrode. A portion of the gate electrode making contact with the gate insulating film has a composition including silicide of metal M expressed with MxSi1-X (0 0.5) in a p-type MOSFET, and is equal to or smaller than 0.5 (X≦0.5) in a n-type MOSFET.
摘要翻译：提供一种半导体器件，其能够解决CMOS晶体管中的阈值控制的问题，伴随着具有高介电常数的栅极绝缘膜和金属栅极电极的组合，并且显着提高性能而不劣化器件的可靠性。半导体器件包括由具有高介电常数的材料构成的栅极绝缘膜和栅电极。与栅极绝缘膜接触的栅电极的一部分具有由MxSi1-X（0 0.5），并且在n型MOSFET中等于或小于0.5（X <= 0.5）。

6. 发明申请

US20100219478A1 MOSFET, METHOD OF FABRICATING THE SAME, CMOSFET, AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译： MOSFET，其制造方法，CMOSFET及其制造方法
公开(公告)号：US20100219478A1
公开(公告)日：2010-09-02
申请号：US12159295
申请日：2006-12-25
申请人： Kenzo Manabe , Nobuyuki Ikarashi
发明人： Kenzo Manabe , Nobuyuki Ikarashi
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/823871 , H01L29/4975 , H01L29/518 , H01L29/7843
摘要： The present invention provides an NMOSFET including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the gate insulating film. The first gate electrode is composed of silicide of a metal M, and at least one element selected as an impurity from a group consisting of sulfur (S), fluorine (F) and chlorine (Cl). The impurity exists as an impurity layer at a surface of the first gate electrode at which the first gate electrode makes contact with the gate insulating film.
摘要翻译：本发明提供一种NMOSFET，其包括半导体衬底，形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的第一栅电极。第一栅电极由金属M的硅化物和由硫（S），氟（F）和氯（Cl）组成的组中选择为至少一种元素的至少一种元素组成。杂质存在于第一栅电极与栅极绝缘膜接触的第一栅电极的表面处的杂质层。

7. 发明申请

US20120181632A1 SEMICONDUCTOR DEVICE AND ITS MANUFACUTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120181632A1
公开(公告)日：2012-07-19
申请号：US13353089
申请日：2012-01-18
申请人： Heiji WATANABE , Kazuhiko Endo , Kenzo Manabe
发明人： Heiji WATANABE , Kazuhiko Endo , Kenzo Manabe
IPC分类号： H01L29/772
CPC分类号： H01L21/28202 , H01L21/28167 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A method of manufacturing a semiconductor device including introducing nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.
摘要翻译：一种在硅衬底上依次具有栅极绝缘膜和栅电极的半导体器件; 其中所述栅极绝缘膜包括含氮的高介电常数绝缘膜，其具有将氮引入金属氧化物或金属硅酸盐中的结构; 含氮高介电常数绝缘膜中的氮浓度在膜厚方向上具有分布; 在与硅衬底相距一定距离的区域存在氮含量高介电常数绝缘膜中的氮浓度在膜厚方向上达到最大的位置。还提供一种制造半导体器件的方法，该半导体器件包括通过用含氮等离子体照射由金属氧化物或金属硅酸盐制成的高介电常数绝缘膜来引入氮。

8. 发明申请

US20050017319A1 Semiconductor device and production method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050017319A1
公开(公告)日：2005-01-27
申请号：US10489522
申请日：2003-03-27
申请人： Kenzo Manabe , Kazuhiko Endo
发明人： Kenzo Manabe , Kazuhiko Endo
IPC分类号： H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L21/469
CPC分类号： H01L21/02244 , H01L21/02178 , H01L21/02247 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： A semiconductor device has an MIS (metal-insulating film-semiconductor) structure, and a film mainly containing Al, O, and N atoms is used on a semiconductor. Alternatively, a semiconductor device has an MIS structure, and a film mainly containing Al, O, and N atoms is provided as a gate insulating film on a channel region between a source and a drain. Characteristics required of a gate insulating film of a 0.05 μm-gate-length-generation semiconductor transistor are satisfied. In particular, no fixed charge is included in the film, and impurity diffusion is reduced.
摘要翻译：半导体器件具有MIS（金属绝缘膜 - 半导体）结构，并且在半导体上使用主要含有Al，O和N原子的膜。或者，半导体器件具有MIS结构，并且在源极和漏极之间的沟道区域上设置主要包含Al，O和N原子的膜作为栅极绝缘膜。满足0.05毫米栅长半导体晶体管的栅极绝缘膜所需的特性。特别地，膜中不包含固定电荷，并且杂质扩散减少。

9. 发明授权

US09343373B2 Semiconductor device including work function adjusting element, and method of manufacturing the same 有权
标题翻译：包括功能调节元件的半导体装置及其制造方法
公开(公告)号：US09343373B2
公开(公告)日：2016-05-17
申请号：US13914956
申请日：2013-06-11
申请人： Kenzo Manabe
发明人： Kenzo Manabe
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823835 , H01L21/28185 , H01L21/823857 , H01L27/092 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/7833
摘要： A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.
摘要翻译：半导体器件具有基板; 以及设置在同一衬底上的N沟道MIS晶体管和P沟道MIS晶体管; N沟道MIS晶体管和P沟道MIS晶体管中的每一个具有包含Hf的高k栅极绝缘膜和设置在高k栅极绝缘膜上的栅电极，N沟道MIS晶体管具有含有设置在基板和高k栅极绝缘膜之间的第一功函数调节元件的氧化硅膜或氧氮化硅膜，以及具有氧化硅膜或氮氧化硅膜的P沟道MIS晶体管，其包括设置在高k栅极绝缘膜和栅电极之间的与N沟道MIS晶体管相同的第一功函数调节元件。

10. 发明授权

US08890289B2 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08890289B2
公开(公告)日：2014-11-18
申请号：US13358133
申请日：2012-01-25
申请人： Kenzo Manabe , Naoya Inoue , Kenichiro Hijioka , Yoshihiro Hayashi
发明人： Kenzo Manabe , Naoya Inoue , Kenichiro Hijioka , Yoshihiro Hayashi
IPC分类号： H01L29/02 , H01L21/02 , H01L27/108 , H01L49/02 , H01L23/532
CPC分类号： H01L27/1085 , H01L21/768 , H01L23/5223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L27/10814 , H01L27/10852 , H01L27/10885 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.
摘要翻译：一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。上部连接线的上表面和盖膜的上表面设置在同一平面上。

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