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1. 发明申请

US20080163029A1 ERROR CORRECTION CODE GENERATION METHOD AND MEMORY CONTROL DEVICE 失效
标题翻译：错误校正代码生成方法和存储器控制器件
公开(公告)号：US20080163029A1
公开(公告)日：2008-07-03
申请号：US11864057
申请日：2007-09-28
申请人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
发明人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
摘要翻译：即使在确认存储的高速缓存行数据不包含错误之后，即使在将存储数据写入高速缓冲存储器（RAM）之前发生RAM错误，也可以生成正确的纠错码。在写入存储数据之前，将用于存储的高速缓存行数据存储在寄存器中，将存储数据写入高速缓冲存储器，将存储的存储内容与存储数据合并，并产生纠错码用于结果的合并。

2. 发明授权

US08533565B2 Cache controller and cache controlling method 失效
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US08533565B2
公开(公告)日：2013-09-10
申请号：US12654442
申请日：2009-12-18
申请人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
发明人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
IPC分类号： G11C29/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F2212/1032
摘要： A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.
摘要翻译：高速缓冲存储器控制单元包括用于维持从执行单元，多个WB，DATA-RAM，FCDR和ECC-RAM接收的8字节存储数据的多个STB。具有这种结构的高速缓冲存储器控制单元从DATA-RAM获得不被存储的数据，将获得的数据存储在FCDR中，并将存储的数据与要存储在存储数据中的数据合并从执行单元输出并存储在STB或WB中以生成新的存储数据。然后，高速缓冲存储器控制单元将所生成的新的存储数据写入DATA-RAM，从新的存储数据生成ECC，并将ECC写入ECC-RAM。

3. 发明授权

US08127205B2 Error correction code generation method and memory control device 失效
标题翻译：纠错码生成方法和存储器控制装置
公开(公告)号：US08127205B2
公开(公告)日：2012-02-28
申请号：US11864057
申请日：2007-09-28
申请人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
发明人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
摘要翻译：即使在确认存储的高速缓存行数据不包含错误之后，即使在将存储数据写入高速缓冲存储器（RAM）之前发生RAM错误，也可以生成正确的纠错码。在写入存储数据之前，将用于存储的高速缓存行数据存储在寄存器中，将存储数据写入高速缓冲存储器，将存储的存储内容与存储数据合并，并产生纠错码用于结果的合并。

4. 发明申请

US20100107038A1 Cache controller and cache controlling method 失效
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US20100107038A1
公开(公告)日：2010-04-29
申请号：US12654442
申请日：2009-12-18
申请人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
发明人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
IPC分类号： H03M13/05 , G06F11/10 , G06F12/08
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F2212/1032
摘要： A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.
摘要翻译：高速缓冲存储器控制单元包括用于维持从执行单元，多个WB，DATA-RAM，FCDR和ECC-RAM接收的8字节存储数据的多个STB。具有这种结构的高速缓冲存储器控制单元从DATA-RAM获得不被存储的数据，将所获得的数据存储在FCDR中，并将存储的数据与要存储在存储数据中的数据合并从执行单元输出并存储在STB或WB中以生成新的存储数据。然后，高速缓冲存储器控制单元将所生成的新的存储数据写入DATA-RAM，从新的存储数据生成ECC，并将ECC写入ECC-RAM。

5. 发明授权

US08856478B2 Arithmetic processing unit, information processing device, and cache memory control method 有权
标题翻译：算术处理单元，信息处理装置和缓存存储器控制方法
公开(公告)号：US08856478B2
公开(公告)日：2014-10-07
申请号：US12929027
申请日：2010-12-22
申请人： Takahito Hirano , Iwao Yamazaki
发明人： Takahito Hirano , Iwao Yamazaki
IPC分类号： G06F12/00 , G06F12/08 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/30047 , G06F9/3824 , G06F12/0859
摘要： A processor holds, in a plurality of respective cache lines, part of data held in a main memory unit. The processor also holds, in the plurality of respective cache lines, a tag address used to search for the data held in the cache lines and a flag indicating the validity of the data held in the cache lines. The processor executes a cache line fill instruction on a cache line corresponding to a specified address. Upon execution of the cache line fill instruction, the processor registers predetermined data in the cache line of the cache memory unit which has a tag address corresponding to the specified address and validates a flag in the cache line having the tag address corresponding to the specified address.
摘要翻译：处理器在多个相应的高速缓存行中保存保存在主存储器单元中的数据的一部分。处理器还在多个相应的高速缓存行中保持用于搜索保存在高速缓存行中的数据的标签地址以及指示保存在高速缓存行中的数据的有效性的标志。处理器在对应于指定地址的高速缓存行上执行高速缓存行填充指令。在执行高速缓存线填充指令时，处理器将高速缓存存储器单元的高速缓存行中的预定数据寄存在具有与指定地址相对应的标签地址的位置，并且在具有对应于指定地址的标签地址的高速缓存行中进行验证。

6. 发明申请

US20060026382A1 Information processor and multi-hit control method 失效
标题翻译：信息处理器和多命中控制方法
公开(公告)号：US20060026382A1
公开(公告)日：2006-02-02
申请号：US10986891
申请日：2004-11-15
申请人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
发明人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/1045
摘要： The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
摘要翻译：本发明包括：用于在多个线程之间共享地址转换缓冲器（TLB = Translation Lookaside Buffer），而不在多线程模式下操作的信息处理器中产生不期望的多命中;地址转换缓冲器，用于存储地址转换对，线程信息，用于从地址转换缓冲器检索与所述虚拟地址相同的虚拟地址的地址转换对用于将虚拟地址转换为物理地址的检索器;确定单元，用于当多个地址转换对由检索者，对应于多个地址转换对的多个线程信息中的两个或更多个所述线程信息是否相同;以及多命中控制器，用于抑制多命中的输出并且如果线程信息被确定则指示执行地址转换根据不同而不同授权单位

7. 发明申请

US20110161600A1 Arithmetic processing unit, information processing device, and cache memory control method 有权
标题翻译：算术处理单元，信息处理装置和缓存存储器控制方法
公开(公告)号：US20110161600A1
公开(公告)日：2011-06-30
申请号：US12929027
申请日：2010-12-22
申请人： Takahito Hirano , Iwao Yamazaki
发明人： Takahito Hirano , Iwao Yamazaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/30047 , G06F9/3824 , G06F12/0859
摘要： A processor holds, in a plurality of respective cache lines, part of data held in a main memory unit. The processor also holds, in the plurality of respective cache lines, a tag address used to search for the data held in the cache lines and a flag indicating the validity of the data held in the cache lines. The processor executes a cache line fill instruction on a cache line corresponding to a specified address. Upon execution of the cache line fill instruction, the processor registers predetermined data in the cache line of the cache memory unit which has a tag address corresponding to the specified address and validates a flag in the cache line having the tag address corresponding to the specified address.
摘要翻译：处理器在多个相应的高速缓存行中保存保存在主存储器单元中的数据的一部分。处理器还在多个相应的高速缓存行中保持用于搜索保存在高速缓存行中的数据的标签地址以及指示保存在高速缓存行中的数据的有效性的标志。处理器在对应于指定地址的高速缓存行上执行高速缓存行填充指令。在执行高速缓存线填充指令时，处理器将高速缓存存储器单元的高速缓存行中的预定数据寄存在具有与指定地址相对应的标签地址的位置，并且在具有对应于指定地址的标签地址的高速缓存行中进行验证。

8. 发明授权

US07617379B2 Multi-hit control method for shared TLB in a multiprocessor system 失效
标题翻译：多处理器系统中共享TLB的多命中控制方法
公开(公告)号：US07617379B2
公开(公告)日：2009-11-10
申请号：US10986891
申请日：2004-11-15
申请人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
发明人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/1045
摘要： The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
摘要翻译：本发明包括：用于在多个线程之间共享地址转换缓冲器（TLB = Translation Lookaside Buffer），而不在多线程模式下操作的信息处理器中产生不期望的多命中;地址转换缓冲器，用于存储地址转换对，线程信息，用于从地址转换缓冲器检索与所述虚拟地址相同的虚拟地址的地址转换对用于将虚拟地址转换为物理地址的检索器;确定单元，用于当多个地址转换对由检索者，对应于多个地址转换对的多个线程信息中的两个或更多个所述线程信息是否相同;以及多命中控制器，用于抑制多命中的输出并且如果线程信息被确定则指示执行地址转换根据不同而不同授权单位

9. 发明授权

US07818545B2 Information processing unit and store instruction control method 有权
标题翻译：信息处理单元和存储指令控制方法
公开(公告)号：US07818545B2
公开(公告)日：2010-10-19
申请号：US10983729
申请日：2004-11-09
申请人： Takashi Miura , Iwao Yamazaki
发明人： Takashi Miura , Iwao Yamazaki
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： In order to increase the operation efficiency of the operation register for holding store data when executing store instructions to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.
摘要翻译：为了在执行存储指令以在主存储器或高速缓冲存储器上的预定存储区域中存储数据时提高用于保存存储数据的操作寄存器的操作效率，在本发明中，指令处理部分被适配为，当保持操作结果的操作寄存器被确定时，使得操作结果从操作寄存器发出以存储缓冲器作为存储数据; 当存储数据在存储指令由存储端口保持之前由存储缓冲器保持时，约束部分限制复位部分在存储指令由存储器保存的时间点将存储数据保持标志设置为OFF 端口将存储数据保持标志保持为ON。

10. 发明申请

US20060026399A1 Information processing unit and store instruction control method 有权
标题翻译：信息处理单元和存储指令控制方法
公开(公告)号：US20060026399A1
公开(公告)日：2006-02-02
申请号：US10983729
申请日：2004-11-09
申请人： Takashi Miura , Iwao Yamazaki
发明人： Takashi Miura , Iwao Yamazaki
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： In order to increase the operation efficiency of the operation register for holding store data when executing store instruction to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined, causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.
摘要翻译：为了在执行存储指令以在主存储器或高速缓冲存储器上的预定存储区域中存储数据时提高用于保存存储数据的操作寄存器的操作效率，在本发明中，指令处理部分被适配成，当确定保持操作结果的操作寄存器时，使得从操作寄存器发出操作结果以将缓冲器存储为存储数据; 当存储数据在存储指令由存储端口保持之前由存储缓冲器保持时，约束部分限制复位部分在存储指令由存储器保存的时间点将存储数据保持标志设置为OFF 端口将存储数据保持标志保持为ON。

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