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1. 发明申请

US20080163029A1 ERROR CORRECTION CODE GENERATION METHOD AND MEMORY CONTROL DEVICE 失效
标题翻译：错误校正代码生成方法和存储器控制器件
公开(公告)号：US20080163029A1
公开(公告)日：2008-07-03
申请号：US11864057
申请日：2007-09-28
申请人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
发明人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
摘要翻译：即使在确认存储的高速缓存行数据不包含错误之后，即使在将存储数据写入高速缓冲存储器（RAM）之前发生RAM错误，也可以生成正确的纠错码。在写入存储数据之前，将用于存储的高速缓存行数据存储在寄存器中，将存储数据写入高速缓冲存储器，将存储的存储内容与存储数据合并，并产生纠错码用于结果的合并。

2. 发明授权

US07818545B2 Information processing unit and store instruction control method 有权
标题翻译：信息处理单元和存储指令控制方法
公开(公告)号：US07818545B2
公开(公告)日：2010-10-19
申请号：US10983729
申请日：2004-11-09
申请人： Takashi Miura , Iwao Yamazaki
发明人： Takashi Miura , Iwao Yamazaki
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： In order to increase the operation efficiency of the operation register for holding store data when executing store instructions to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.
摘要翻译：为了在执行存储指令以在主存储器或高速缓冲存储器上的预定存储区域中存储数据时提高用于保存存储数据的操作寄存器的操作效率，在本发明中，指令处理部分被适配为，当保持操作结果的操作寄存器被确定时，使得操作结果从操作寄存器发出以存储缓冲器作为存储数据; 当存储数据在存储指令由存储端口保持之前由存储缓冲器保持时，约束部分限制复位部分在存储指令由存储器保存的时间点将存储数据保持标志设置为OFF 端口将存储数据保持标志保持为ON。

3. 发明申请

US20060026399A1 Information processing unit and store instruction control method 有权
标题翻译：信息处理单元和存储指令控制方法
公开(公告)号：US20060026399A1
公开(公告)日：2006-02-02
申请号：US10983729
申请日：2004-11-09
申请人： Takashi Miura , Iwao Yamazaki
发明人： Takashi Miura , Iwao Yamazaki
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： In order to increase the operation efficiency of the operation register for holding store data when executing store instruction to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined, causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.
摘要翻译：为了在执行存储指令以在主存储器或高速缓冲存储器上的预定存储区域中存储数据时提高用于保存存储数据的操作寄存器的操作效率，在本发明中，指令处理部分被适配成，当确定保持操作结果的操作寄存器时，使得从操作寄存器发出操作结果以将缓冲器存储为存储数据; 当存储数据在存储指令由存储端口保持之前由存储缓冲器保持时，约束部分限制复位部分在存储指令由存储器保存的时间点将存储数据保持标志设置为OFF 端口将存储数据保持标志保持为ON。

4. 发明授权

US06981121B2 Method for aligning stored data 失效
标题翻译：存储数据对齐的方法
公开(公告)号：US06981121B2
公开(公告)日：2005-12-27
申请号：US10350115
申请日：2003-01-24
申请人： Takashi Miura , Iwao Yamazaki
发明人： Takashi Miura , Iwao Yamazaki
IPC分类号： G06F9/30 , G06F9/315 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/3824 , G06F12/0886
摘要： An arithmetic unit performs an arithmetic operation, and outputs data obtained as a result of the arithmetic operation. The data output from the arithmetic unit is stored in a store buffer. The data read from the store buffer is stored in cache memory. A first alignment circuit allows an alignment circuit to realign the data output from the arithmetic unit and stored in the store buffer, and the second alignment circuit realigns data read from the store buffer and stored in the cache memory.
摘要翻译：算术单元执行算术运算，并输出作为运算结果得到的数据。从运算单元输出的数据存储在存储缓冲器中。从存储缓冲器读取的数据存储在高速缓冲存储器中。第一对准电路允许对准电路将从运算单元输出的数据重新排列并存储在存储缓冲器中，并且第二对准电路重新排列从存储缓冲器读取并存储在高速缓冲存储器中的数据。

5. 发明授权

US08533565B2 Cache controller and cache controlling method 失效
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US08533565B2
公开(公告)日：2013-09-10
申请号：US12654442
申请日：2009-12-18
申请人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
发明人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
IPC分类号： G11C29/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F2212/1032
摘要： A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.
摘要翻译：高速缓冲存储器控制单元包括用于维持从执行单元，多个WB，DATA-RAM，FCDR和ECC-RAM接收的8字节存储数据的多个STB。具有这种结构的高速缓冲存储器控制单元从DATA-RAM获得不被存储的数据，将获得的数据存储在FCDR中，并将存储的数据与要存储在存储数据中的数据合并从执行单元输出并存储在STB或WB中以生成新的存储数据。然后，高速缓冲存储器控制单元将所生成的新的存储数据写入DATA-RAM，从新的存储数据生成ECC，并将ECC写入ECC-RAM。

6. 发明授权

US08127205B2 Error correction code generation method and memory control device 失效
标题翻译：纠错码生成方法和存储器控制装置
公开(公告)号：US08127205B2
公开(公告)日：2012-02-28
申请号：US11864057
申请日：2007-09-28
申请人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
发明人： Takahito Hirano , Takashi Miura , Iwao Yamazaki
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
摘要翻译：即使在确认存储的高速缓存行数据不包含错误之后，即使在将存储数据写入高速缓冲存储器（RAM）之前发生RAM错误，也可以生成正确的纠错码。在写入存储数据之前，将用于存储的高速缓存行数据存储在寄存器中，将存储数据写入高速缓冲存储器，将存储的存储内容与存储数据合并，并产生纠错码用于结果的合并。

7. 发明申请

US20100107038A1 Cache controller and cache controlling method 失效
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US20100107038A1
公开(公告)日：2010-04-29
申请号：US12654442
申请日：2009-12-18
申请人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
发明人： Takashi Miura , Iwao Yamazaki , Takahito Hirano
IPC分类号： H03M13/05 , G06F11/10 , G06F12/08
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F2212/1032
摘要： A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.
摘要翻译：高速缓冲存储器控制单元包括用于维持从执行单元，多个WB，DATA-RAM，FCDR和ECC-RAM接收的8字节存储数据的多个STB。具有这种结构的高速缓冲存储器控制单元从DATA-RAM获得不被存储的数据，将所获得的数据存储在FCDR中，并将存储的数据与要存储在存储数据中的数据合并从执行单元输出并存储在STB或WB中以生成新的存储数据。然后，高速缓冲存储器控制单元将所生成的新的存储数据写入DATA-RAM，从新的存储数据生成ECC，并将ECC写入ECC-RAM。

8. 发明授权

US08468397B2 Error controlling system, processor and error injection method 有权
标题翻译：错误控制系统，处理器和错误注入方法
公开(公告)号：US08468397B2
公开(公告)日：2013-06-18
申请号：US12974336
申请日：2010-12-21
申请人： Iwao Yamazaki
发明人： Iwao Yamazaki
IPC分类号： G06F11/00 , H04L1/24
CPC分类号： H04L1/241 , G06F11/2215 , G06F11/267
摘要： An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.
摘要翻译：误差控制系统包括多个误差产生目标电路，多个伪误差产生装置，每个具有保持定向伪误差内容的伪误差内容保持寄存器，每个伪误差产生装置产生与伪伪对象相对应的伪误差在要被写入多个错误产生目标电路之一的数据中的至少一个中保存在相应的伪错误内容保持寄存器中的错误内容以及在被指示生成时将从多个错误产生目标电路之一读取的数据所述伪错误控制装置和伪错误控制装置，其指示所述多个伪错误生成装置生成与在所述多个伪错误中的每一个中提供的所述伪错误内容保持寄存器中的每一个中保持的各个伪错误内容相对应的伪错误生成设备。

9. 发明申请

US20120253246A1 TAPPING DEVICE FOR PRODUCING BEAUTIFUL SKIN 有权
标题翻译：用于生产美容皮肤的切割装置
公开(公告)号：US20120253246A1
公开(公告)日：2012-10-04
申请号：US13509148
申请日：2011-11-21
申请人： Iwao Yamazaki , Kazunori Yamanaka
发明人： Iwao Yamazaki , Kazunori Yamanaka
IPC分类号： A61H23/02
CPC分类号： A61H23/006 , A61H39/04 , A61H2201/1215 , A61H2201/149 , A61H2201/1664 , A61H2201/1685 , A61H2201/5043 , A61N1/0428 , A61N1/303
摘要： In the tapping device for producing beautiful skin, a Head contacts with skin. A Tapping mechanism pats the skin facing the Head with a Pad. The Tapping mechanism is equipped with the Pad at one end, and has a Shaft from which the Head projects and rolls back by piston actions. A Biasing member biases the Shaft toward one side of the piston actions. A Wire rod empowers the Shaft towards the direction resisting the biasing power of the Biasing member when tension is provided. An Actuator provides tension intermittently in a Wire rod, the tension of the wire rod and biasing of the bias member providing piston actions.
摘要翻译：在用于生产美丽皮肤的攻丝装置中，头部与皮肤接触。攻丝机构用垫子拍打面对头部的皮肤。攻丝机构在一端配备了垫，并具有一个轴，头部通过活塞活动弹出并回滚。偏心构件将轴朝向活塞的一侧偏压。当提供张力时，线杆使轴向抵抗偏压构件的偏置力的方向。致动器在线棒中间歇地提供张力，线材的张力和偏置构件的偏压提供活塞动作。

10. 发明授权

US07819782B2 Exercise machine 有权
标题翻译：运动机
公开(公告)号：US07819782B2
公开(公告)日：2010-10-26
申请号：US11812009
申请日：2007-06-14
申请人： Iwao Yamazaki
发明人： Iwao Yamazaki
IPC分类号： A63B69/08 , A63B21/068 , A63B21/008
CPC分类号： A63B69/06 , A63B21/0087 , A63B22/0012 , A63B22/205 , A63B23/0211 , A63B2022/0033 , A63B2022/0038 , A63B2208/0238 , A63B2225/09
摘要： An exercise machine includes a supporting stage; a saddle arranged relatively for said supporting stage; a pedaling stage with a pair of pedals arranged relatively for said supporting stage; and a handle arranged relatively for said supporting stage. The pedaling stage is configured such that the pair of pedals are connected with one another via a first air pump.
摘要翻译：运动器械包括支撑台; 相对于所述支撑台布置的鞍座; 一个踩踏台，一对相对于所述支撑台排列的踏板; 以及相对于所述支撑台布置的手柄。蹬踏台构造成使得该对踏板通过第一气泵相互连接。

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