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1. 发明申请

US20070147137A1 Memory Control Circuit and Memory Control Method 有权
标题翻译：存储器控制电路和存储器控制方法
公开(公告)号：US20070147137A1
公开(公告)日：2007-06-28
申请号：US11614793
申请日：2006-12-21
申请人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
发明人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
IPC分类号： G11C7/10
CPC分类号： G06F12/04
摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.
摘要翻译：一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器）指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写数据。

2. 发明申请

US20070146194A1 Encoding Circuit and Digital Signal Processing Circuit 有权
标题翻译：编码电路和数字信号处理电路
公开(公告)号：US20070146194A1
公开(公告)日：2007-06-28
申请号：US11614821
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G08C19/12
CPC分类号： H04L1/0043
摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.
摘要翻译：公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

3. 发明授权

US07440338B2 Memory control circuit and memory control method 有权
标题翻译：存储器控制电路和存储器控制方法
公开(公告)号：US07440338B2
公开(公告)日：2008-10-21
申请号：US11614793
申请日：2006-12-21
申请人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
发明人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
IPC分类号： G11C7/10
CPC分类号： G06F12/04
摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.
摘要翻译：一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器）指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写数据。

4. 发明授权

US07885989B2 Encoding circuit and digital signal processing circuit 有权
标题翻译：编码电路和数字信号处理电路
公开(公告)号：US07885989B2
公开(公告)日：2011-02-08
申请号：US11614821
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F7/00
CPC分类号： H04L1/0043
摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.
摘要翻译：公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

5. 发明申请

US20070150641A1 Bus Address Selecting Circuit and Bus Address Selecting Method 审中-公开
标题翻译：总线地址选择电路和总线地址选择方法
公开(公告)号：US20070150641A1
公开(公告)日：2007-06-28
申请号：US11614807
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F9/30043 , G06F9/30145 , G06F9/3824
摘要： A bus address selecting circuit is disclosed that selects addresses to be output to a first address bus connected to a first memory and a second address bus connected to a second memory, the bus address selecting circuit comprising an address output circuit that, based on a selecting bit composed of a predetermined plurality of bits in an instruction code, outputs addresses stored in first and second address registers out of a plurality of address registers as first and second addresses; and a bus selecting circuit that, based on predetermined higher-order n bits of at least one of the first and second addresses, outputs the first address to one of the first and second address buses and the second address to the other of the first and second address buses.
摘要翻译：公开了一种总线地址选择电路，其选择要输出到连接到第一存储器的第一地址总线的地址和连接到第二存储器的第二地址总线，总线地址选择电路包括地址输出电路，其基于选择在指令码中由预定的多个比特组成的比特，将从多个地址寄存器中存储的第一和第二地址寄存器中存储的地址作为第一和第二地址输出; 以及总线选择电路，其基于所述第一和第二地址中的至少一个的预定高阶n位，将所述第一地址输出到所述第一和第二地址总线中的一个，并将所述第二地址输出到所述第一和第二地址总线中的第一地址，第二地址总线。

6. 发明授权

US07380476B2 Gas sampling bag 有权
标题翻译：气体取样袋
公开(公告)号：US07380476B2
公开(公告)日：2008-06-03
申请号：US10913668
申请日：2004-08-06
申请人： Hitoshi Hirai , Hideki Ohashi , Toshio Mizutaka , Kimikazu Yoda , Kenichi Uchida , Hiroaki Katumata
发明人： Hitoshi Hirai , Hideki Ohashi , Toshio Mizutaka , Kimikazu Yoda , Kenichi Uchida , Hiroaki Katumata
IPC分类号： G01N1/12
CPC分类号： G01N1/2252 , G01N2001/2264
摘要： A gas sampling bag is capable of blowing out the gas uniformly into the bag main body, and filling the bag main body with gas in a securely mixed state. A gas sampling bag that is connected to a constant volume sampling passage, contains a pipe, on which a plurality of gas inlet/outlet holes are formed, in a bag main body, and allows the gas to flow into/out of the bag main body through the gas inlet/outlet holes. The opening of the plurality of gas inlet/outlet holes is formed in such a manner that the size is minimized while the pressure loss is suppressed so as not to increase as far as possible.
摘要翻译：气体取样袋能够将气体均匀地吹出到袋主体中，并且以可靠的混合状态用气体填充袋主体。连接到恒定体积采样通道的气体取样袋在袋主体中容纳有形成有多个气体入口/出口孔的管道，并且允许气体流入/流出袋主体身体通过气体入口/出口孔。多个气体入口/出口孔的开口形成为尽可能减小压力损失的尺寸，尽可能不增加。

7. 发明授权

US07358875B2 Echo preventing circuit and digital signal processing circuit 有权
标题翻译：回波防止电路和数字信号处理电路
公开(公告)号：US07358875B2
公开(公告)日：2008-04-15
申请号：US11627839
申请日：2007-01-26
申请人： Takeo Inoue , Hideki Ohashi
发明人： Takeo Inoue , Hideki Ohashi
IPC分类号： H03M1/00
CPC分类号： H04M9/082 , H04B3/23
摘要： An echo preventing circuit comprises a filter that is inputted with a first digital signal and outputs a second and a third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; and an AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, wherein the filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and wherein the fourth analog signal outputted from the subtracting circuit is outputted as an output signal corresponding to the third analog signal.
摘要翻译：回波防止电路包括输入第一数字信号并输出第二和第三数字信号的滤波器; 第一DA转换器，将第二数字信号转换为第一模拟信号并输出第一模拟信号; 第二DA转换器，其将第三数字信号转换为第二模拟信号并输出第二模拟信号; 输出/输出端子，其输出第一模拟信号或输入第三模拟信号; 减法电路，输出从通过组合所述第一模拟信号和所述第三模拟信号而形成的信号中减去所述第二模拟信号而获得的第四模拟信号; 以及AD转换器，其将第四模拟信号转换为第四数字信号并输出第四数字信号，其中滤波器设置通过从形成的信号中去除或衰减第一模拟信号而形成的第四模拟信号的滤波器系数当第三模拟信号不存在时，通过将第一模拟信号和第三模拟信号组合在基于从AD转换器输出的第四数字信号输入到第一和第二DA转换器中，并且其中第四模拟信号输出从减法电路输出的与第三模拟信号对应的输出信号。

8. 发明申请

US20070176812A1 Echo Preventing Circuit and Digital Signal Processing Circuit 有权
标题翻译：回波预防电路和数字信号处理电路
公开(公告)号：US20070176812A1
公开(公告)日：2007-08-02
申请号：US11627839
申请日：2007-01-26
申请人： Takeo Inoue , Hideki Ohashi
发明人： Takeo Inoue , Hideki Ohashi
IPC分类号： H03M1/66
CPC分类号： H04M9/082 , H04B3/23
摘要： An echo preventing circuit comprises a filter that is inputted with a first digital signal and outputs a second and a third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; and an AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, wherein the filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and wherein the fourth analog signal outputted from the subtracting circuit is outputted as an output signal corresponding to the third analog signal.
摘要翻译：回波防止电路包括输入第一数字信号并输出第二和第三数字信号的滤波器; 第一DA转换器，将第二数字信号转换为第一模拟信号并输出第一模拟信号; 第二DA转换器，其将第三数字信号转换为第二模拟信号并输出第二模拟信号; 输出/输出端子，其输出第一模拟信号或输入第三模拟信号; 减法电路，输出从通过组合所述第一模拟信号和所述第三模拟信号而形成的信号中减去所述第二模拟信号而获得的第四模拟信号; 以及AD转换器，其将第四模拟信号转换为第四数字信号并输出第四数字信号，其中滤波器设置通过从形成的信号中去除或衰减第一模拟信号而形成的第四模拟信号的滤波器系数当第三模拟信号不存在时，通过将第一模拟信号和第三模拟信号组合在基于从AD转换器输出的第四数字信号输入到第一和第二DA转换器中，并且其中第四模拟信号输出从减法电路输出的与第三模拟信号对应的输出信号。

9. 发明申请

US20070154022A1 Echo Cancellation Circuit 审中-公开
标题翻译：回波消除电路
公开(公告)号：US20070154022A1
公开(公告)日：2007-07-05
申请号：US11614812
申请日：2006-12-21
申请人： Akira Iketani , Hideki Ohashi
发明人： Akira Iketani , Hideki Ohashi
IPC分类号： H04B3/20
CPC分类号： H04B3/232
摘要： An echo cancellation circuit that cancels echo generated when an earphone-microphone is used, the earphone-microphone converting an input first analog signal into voice to be output and converting input voice into a second analog signal to be output, the circuit comprising: a cancellation circuit that receives input of first and second analog signals at a first input terminal and input of a third analog signal at a second input terminal, the third analog signal being generated depending on the first analog signal to prevent the first analog signal from being output along with the second analog signal, and that cancels the first analog signal included in the first and second analog signals with the third analog signal to output the first and second analog signals with the first analog signal canceled; a first load circuit disposed between the earphone-microphone and the first input terminal; and a second load circuit corresponding to the first load circuit and a third load circuit corresponding to the impedance of the earphone-microphone, the second and third load circuits being disposed on the side of the second input terminal.
摘要翻译：一种回声消除电路，其消除使用耳机麦克风时产生的回波，所述耳机麦克风将输入的第一模拟信号转换为语音以输出，并将输入的语音转换为要输出的第二模拟信号，所述电路包括：取消电路，其在第一输入端接收第一和第二模拟信号的输入，并在第二输入端输入第三模拟信号，第三模拟信号根据第一模拟信号产生，以防止第一模拟信号沿着利用所述第二模拟信号，并且利用所述第三模拟信号来取消包括在所述第一和第二模拟信号中的所述第一模拟信号，以在所述第一模拟信号被取消的情况下输出所述第一和第二模拟信号; 设置在所述耳机麦克风和所述第一输入端子之间的第一负载电路; 以及对应于第一负载电路的第二负载电路和对应于耳机麦克风的阻抗的第三负载电路，第二和第三负载电路设置在第二输入端的一侧。

10. 发明授权

US6142026A Wheel information estimating apparatus 失效
标题翻译：车轮信息估计装置
公开(公告)号：US6142026A
公开(公告)日：2000-11-07
申请号：US458099
申请日：1995-06-01
申请人： Hideki Ohashi , Hiroyuki Kawai , Hiroyoshi Kojima , Takaji Umeno , Katsuhiro Asano , Toshiharu Naito , Nobuyoshi Onogi
发明人： Hideki Ohashi , Hiroyuki Kawai , Hiroyoshi Kojima , Takaji Umeno , Katsuhiro Asano , Toshiharu Naito , Nobuyoshi Onogi
IPC分类号： B60C23/06 , G01M15/00 , B60C23/00 , G01L17/00
CPC分类号： B60C23/062 , B60C23/061
摘要： A wheel information estimating apparatus, which includes: a detecting device for detecting a wheel motion state relating to a movement of a tired wheel of a motor vehicle; an estimating device for estimating wheel information relating to the tired wheel, on the basis of the wheel motion state detected by the detecting device; and a modifying device for modifying an element relating to estimation of the wheel information, so as to improve an accuracy of estimating the wheel information. The element to be modified is selected from a movement of a center of rotation of the tired wheel as viewed in a plane in which the wheel is rotated, a signal applied from the detecting device to the estimating device, and an internal parameter used by the estimating means for estimating the wheel information.
摘要翻译：一种车轮信息估计装置，包括：检测装置，用于检测与机动车辆的轮胎的运动有关的车轮运动状态; 基于由所述检测装置检测到的车轮运动状态来估计与所述轮胎相关的车轮信息的估计装置; 以及用于修改与车轮信息的估计有关的元件的修改装置，以便提高车轮信息的估计精度。要修改的元件选自在车轮旋转的平面中观察到的轮胎的旋转中心的运动，从检测装置施加到估计装置的信号，以及由用于估计车轮信息的估计装置。

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