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1. 发明申请

US20110318697A1 GROUND FLARE 审中-公开
标题翻译：接地火花
公开(公告)号：US20110318697A1
公开(公告)日：2011-12-29
申请号：US13141266
申请日：2009-12-18
申请人： Katsuhiko Yokohama , Iwao Honda , Naoki Suganuma , Hirofumi Ando , Naoshige Yoshida , Yoshihiko Horie , Hitoshi Terada , Toru Kawai , Atsushi Kimura
发明人： Katsuhiko Yokohama , Iwao Honda , Naoki Suganuma , Hirofumi Ando , Naoshige Yoshida , Yoshihiko Horie , Hitoshi Terada , Toru Kawai , Atsushi Kimura
IPC分类号： F23G7/08
CPC分类号： F23G7/085 , F23D2210/00 , F23J2900/13003 , F23M20/005
摘要： Provided is a ground flare in which a low-frequency vibration generated from a ground flare tower, such as a chimney, is properly adjusted to suppress it below a fixture-vibration generation limit, thereby preventing surrounding objects from resonating and vibrating. In a ground flare that burns a flammable exhaust gas with a burner at the lower end of a chimney, in which the lower end of the chimney and the periphery of the burner are surrounded by a windbreak, the low-frequency-noise sound pressure level of a ground flare tower composed of the chimney and the windbreak is reduced by selecting at least one of changing a natural frequency generated from the ground flare tower, using multiple ground flare towers, and installing a low-frequency-vibration absorber in the ground flare tower.
摘要翻译：提供了一种地面火炬，其中适当地调节从诸如烟囱的地面火炬塔产生的低频振动以将其抑制在低于固定装置 - 振动产生极限，从而防止周围物体发生共振和振动。在烟囱下端用燃烧器燃烧可燃废气的地面火炬中，烟囱的下端和燃烧器的周边被防风包围，低频噪声声压级由烟囱和防风林组成的地面火炬塔通过选择至少一个改变地面火炬塔产生的固有频率，使用多个地面火炬塔，并在地面火炬中安装低频振动吸收器塔。

2. 发明授权

US07502900B2 Data processing integrated circuit including a memory transfer controller 有权
标题翻译：数据处理集成电路，包括存储器传输控制器
公开(公告)号：US07502900B2
公开(公告)日：2009-03-10
申请号：US11315593
申请日：2005-12-23
申请人： Iwao Honda
发明人： Iwao Honda
IPC分类号： G06F12/02 , G06F12/00 , G06F13/00
CPC分类号： G06F13/28 , G06F2213/0038
摘要： A data processing integrated circuit comprises a CPU, a memory that stores a program for controlling the CPU, a memory transfer controller for sending/receiving data to/from an external memory provided external to the data processing integrated circuit, and a read address storing section into which an address of data in the external memory is set by the CPU controlled by the program stored in the memory, which data is to be used at a later stage than a process being executed by the CPU, wherein the memory transfer controller transfers the data stored at the address in the external memory to the memory.
摘要翻译：数据处理集成电路包括CPU，存储用于控制CPU的程序的存储器，用于向/从外部提供数据处理集成电路的外部存储器发送/接收数据的存储器传送控制器以及读取地址存储部分其中由存储在存储器中的程序控制的CPU设置外部存储器中的数据地址，该数据将在比CPU执行的处理更晚的阶段被使用，其中存储器传送控制器将数据存储在外部存储器中的地址到存储器。

3. 发明申请

US20080301401A1 Processor 有权
标题翻译：处理器
公开(公告)号：US20080301401A1
公开(公告)日：2008-12-04
申请号：US12128325
申请日：2008-05-28
申请人： Iwao Honda , Shinya Kishida
发明人： Iwao Honda , Shinya Kishida
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30134
摘要： A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.
摘要翻译：处理器包括：多个寄存器; 指令读出电路，被配置为从存储器读出指令; 如果由指令读出电路读出的指令是存储在多个寄存器中的每一个的数据的指令，则指令生成电路被配置为产生用于各个寄存器的用于将数据保存到预定存储区域中的指令; 以及指令执行电路，被配置为执行从存储器读出的指令和由指令产生电路产生的指令。

4. 发明申请

US20070296620A1 Data processing integrated circuit 有权
标题翻译：数据处理集成电路
公开(公告)号：US20070296620A1
公开(公告)日：2007-12-27
申请号：US11315593
申请日：2005-12-23
申请人： Iwao Honda
发明人： Iwao Honda
IPC分类号： G06F13/14 , H03M1/12
CPC分类号： G06F13/28 , G06F2213/0038
摘要： A data processing integrated circuit comprises a CPU, a memory that stores a program for controlling the CPU, a memory transfer controller for sending/receiving data to/from an external memory provided external to the data processing integrated circuit, and a read address storing section into which an address of data in the external memory is set by the CPU controlled by the program stored in the memory, which data is to be used at a later stage than a process being executed by the CPU, wherein the memory transfer controller transfers the data stored at the address in the external memory to the memory.
摘要翻译：数据处理集成电路包括CPU，存储用于控制CPU的程序的存储器，用于向/从外部提供数据处理集成电路的外部存储器发送/接收数据的存储器传送控制器以及读取地址存储部分其中由存储在存储器中的程序控制的CPU设置外部存储器中的数据地址，该数据将在比CPU执行的处理更晚的阶段被使用，其中存储器传送控制器将数据存储在外部存储器中的地址到存储器。

5. 发明授权

US07440338B2 Memory control circuit and memory control method 有权
标题翻译：存储器控制电路和存储器控制方法
公开(公告)号：US07440338B2
公开(公告)日：2008-10-21
申请号：US11614793
申请日：2006-12-21
申请人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
发明人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
IPC分类号： G11C7/10
CPC分类号： G06F12/04
摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.
摘要翻译：一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器）指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写数据。

6. 发明申请

US20070242533A1 Memory Access Apparatus 有权
标题翻译：存储器访问装置
公开(公告)号：US20070242533A1
公开(公告)日：2007-10-18
申请号：US11734749
申请日：2007-04-12
申请人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
发明人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C8/06
摘要： A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.
摘要翻译：从存储器读取数据的存储器访问装置，包括输入地址信息的终端的存储器，输入了以预定周期改变的时钟信号的终端，读取命令被输入的终端，以及终端根据读取命令，在时钟信号从一个电平变化到另一个电平的定时，输出存储在由地址信息识别的地址的数据，该存储器访问装置包括：地址信息输出单元，其输出地址信息以及所述读取命令在所述时钟信号从所述一个级别改变到另一个级别的第一定时; 以及读取数据存储单元，其在时钟信号从一个电平变化到另一个电平的第一定时之后的第二定时存储从存储器输出的数据，读取数据存储单元在第二时间之后的第三定时存储数据时钟信号从一个电平变化到另一个电平的时序。

7. 发明授权

US07885989B2 Encoding circuit and digital signal processing circuit 有权
标题翻译：编码电路和数字信号处理电路
公开(公告)号：US07885989B2
公开(公告)日：2011-02-08
申请号：US11614821
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F7/00
CPC分类号： H04L1/0043
摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.
摘要翻译：公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

8. 发明申请

US20080307032A1 Divider Circuit 审中-公开
标题翻译：分频电路
公开(公告)号：US20080307032A1
公开(公告)日：2008-12-11
申请号：US12136542
申请日：2008-06-10
申请人： Iwao Honda
发明人： Iwao Honda
IPC分类号： G06F7/535
CPC分类号： G06F7/537 , G06F2207/5353
摘要： A divider circuit for dividing a dividend by a divisor, includes: a multiplicative divisor generating circuit configured to generate 2m-2 multiplicative divisors that are 2 to 2m-1 times the divisor, the m indicating an integer of 2 or more; and a quotient generating circuit configured to sequentially generate a quotient of the dividend, by m bits in decreasing order of significance, by subtracting from the dividend the divisor and the 2m-2 multiplicative divisors, respectively.
摘要翻译：一个用于除数除数的除数的除法器电路，包括：乘法除数产生电路，被配置为产生2乘以2乘法乘数的乘法除数，m表示2或更大的整数; 商产生电路被配置为通过从除数分别除以除数和2m-2乘数除数来顺序地以有意义的递减顺序产生除以m比特的乘数的商。

9. 发明申请

US20070150641A1 Bus Address Selecting Circuit and Bus Address Selecting Method 审中-公开
标题翻译：总线地址选择电路和总线地址选择方法
公开(公告)号：US20070150641A1
公开(公告)日：2007-06-28
申请号：US11614807
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F9/30043 , G06F9/30145 , G06F9/3824
摘要： A bus address selecting circuit is disclosed that selects addresses to be output to a first address bus connected to a first memory and a second address bus connected to a second memory, the bus address selecting circuit comprising an address output circuit that, based on a selecting bit composed of a predetermined plurality of bits in an instruction code, outputs addresses stored in first and second address registers out of a plurality of address registers as first and second addresses; and a bus selecting circuit that, based on predetermined higher-order n bits of at least one of the first and second addresses, outputs the first address to one of the first and second address buses and the second address to the other of the first and second address buses.
摘要翻译：公开了一种总线地址选择电路，其选择要输出到连接到第一存储器的第一地址总线的地址和连接到第二存储器的第二地址总线，总线地址选择电路包括地址输出电路，其基于选择在指令码中由预定的多个比特组成的比特，将从多个地址寄存器中存储的第一和第二地址寄存器中存储的地址作为第一和第二地址输出; 以及总线选择电路，其基于所述第一和第二地址中的至少一个的预定高阶n位，将所述第一地址输出到所述第一和第二地址总线中的一个，并将所述第二地址输出到所述第一和第二地址总线中的第一地址，第二地址总线。

10. 发明授权

US08255672B2 Single instruction decode circuit for decoding instruction from memory and instructions from an instruction generation circuit 有权
标题翻译：用于从存储器解码指令的单指令解码电路和来自指令生成电路的指令
公开(公告)号：US08255672B2
公开(公告)日：2012-08-28
申请号：US12128325
申请日：2008-05-28
申请人： Iwao Honda , Shinya Kishida
发明人： Iwao Honda , Shinya Kishida
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F9/46
CPC分类号： G06F9/3004 , G06F9/30134
摘要： A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.
摘要翻译：处理器包括：多个寄存器; 指令读出电路，被配置为从存储器读出指令; 如果由指令读出电路读出的指令是存储在多个寄存器中的每一个的数据的指令，则指令生成电路被配置为产生用于各个寄存器的用于将数据保存到预定存储区域中的指令; 以及指令执行电路，被配置为执行从存储器读出的指令和由指令产生电路产生的指令。

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