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1. 发明申请

US20080098190A1 NON-VOLATILE STORAGE DEVICE 有权
标题翻译：非易失存储器件
公开(公告)号：US20080098190A1
公开(公告)日：2008-04-24
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

2. 发明申请

US20070198770A1 Memory system and memory card 审中-公开
公开(公告)号：US20070198770A1
公开(公告)日：2007-08-23
申请号：US11730089
申请日：2007-03-29
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

3. 发明申请

US20050015539A1 Memory system and memory card 有权
标题翻译：内存系统和存储卡
公开(公告)号：US20050015539A1
公开(公告)日：2005-01-20
申请号：US10500252
申请日：2002-01-09
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G11C7/10 , G11C16/02 , G11C16/10
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.
摘要翻译：存储器系统包括多个非易失性存储器芯片（CHP1和CHP2），每个非易失性存储器芯片具有可以执行彼此独立的存储器操作的多个存储器组（BNK1和BNK2）和可以控制访问每个存储器的所述非易失性存储器芯片。存储器控制器可以选择性地指示在非易失性存储器芯片的多个存储体上的同时写入操作或交错写入操作。因此，在同时写入操作中，可以完全并行地执行比写入建立时间长得多的写入操作。在交错写入操作中，可以执行写入设置之后的写入操作，以便部分地与另一个存储体上的写入操作重叠。结果，可以使构成高速写入操作的存储器系统的非易失性存储器芯片的数量相对较小。

4. 发明授权

US07334080B2 Nonvolatile memory with independent access capability to associated buffer 有权
标题翻译：非易失性存储器，具有对相关缓冲区的独立访问能力
公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

5. 发明授权

US07290109B2 Memory system and memory card 有权
标题翻译：内存系统和存储卡
公开(公告)号：US07290109B2
公开(公告)日：2007-10-30
申请号：US10500252
申请日：2002-01-09
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.
摘要翻译：存储器系统包括多个非易失性存储器芯片（CHP 1和CHP 2），每个非易失性存储器芯片具有可独立于彼此执行存储器操作的多个存储器组（BNK 1和BNK 2）和存储器控制器（5）控制以访问每个所述非易失性存储器芯片。存储器控制器可以选择性地指示在非易失性存储器芯片的多个存储体上的同时写入操作或交错写入操作。因此，在同时写入操作中，可以完全并行地执行比写入建立时间长得多的写入操作。在交错写入操作中，可以执行写入设置之后的写入操作，以便部分地与另一个存储体上的写入操作重叠。结果，可以使构成高速写入操作的存储器系统的非易失性存储器芯片的数量相对较小。

6. 发明申请

US20050228962A1 Non-volatile storage device 有权
标题翻译：非易失性存储设备
公开(公告)号：US20050228962A1
公开(公告)日：2005-10-13
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F13/00 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

7. 发明授权

US07581058B2 Non-volatile memory having multiple erase operations 有权
标题翻译：具有多次擦除操作的非易失性存储器
公开(公告)号：US07581058B2
公开(公告)日：2009-08-25
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

8. 发明授权

US07072225B2 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US07072225B2
公开(公告)日：2006-07-04
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

9. 发明授权

US06459621B1 Semiconductor integrated circuit and data processing system 失效
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US06459621B1
公开(公告)日：2002-10-01
申请号：US09931030
申请日：2001-08-17
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
摘要翻译：闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制，直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。控制涉及第一写入模式（粗写），其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高，并且第二写入模式（高精度写入），其中阈值电压的变化量相对低。与高精度模式相比，改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。因此，使用粗写入模式时的验证操作数量很少，因此可以加快整个写入操作。

10. 发明授权

US06930924B2 Nonvolatile memory and method of programming the same memory 有权
标题翻译：非易失性存储器和编程相同存储器的方法
公开(公告)号：US06930924B2
公开(公告)日：2005-08-16
申请号：US10404101
申请日：2003-04-02
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
摘要翻译：提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电，公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

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