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    • 1. 发明授权
    • Phosphorescent phosphor
    • 磷光荧光粉
    • US5951915A
    • 1999-09-14
    • US101762
    • 1998-07-20
    • Takashi HaseNoboru KoteraMorio HayakawaNorio MiuraHitoshi Sakamoto
    • Takashi HaseNoboru KoteraMorio HayakawaNorio MiuraHitoshi Sakamoto
    • C09K11/77C09K11/59C09K11/66
    • C09K11/7792C09K11/7793
    • A phosphorescent phosphor represented by m(Sr.sub.1-a,M.sup.1.sub.a)O.n(Mg.sub.1-b, M.sup.2.sub.b)O.2(Si.sub.1-c,Ge.sub.c)O.sub.2 :Eu.sub.x Ln.sub.y, wherein M.sup.1 is Ca and/or Ba, M.sup.2 Be, Zn and/or Cd, Ln is Sc, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, B, Al, Ga, In, Tl, Sb, Bi, As, P, Sn, Pb, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Cr and/or Mn, and wherein a, b, c, m, n, x and y are within ranges of 0.ltoreq.a.ltoreq.0.8, 0.ltoreq.b.ltoreq.0.2, 0.ltoreq.c.ltoreq.0.2, 1.5.ltoreq.m.ltoreq.3.5, 0.5.ltoreq.n.ltoreq.1.5. 1.times.10.sup.-5 .ltoreq.x.ltoreq.1.times.10.sup.-1, and 1.times.10.sup.-5 .ltoreq.y.ltoreq.1.times.10.sup.-1, and which contains a halogen element such as F, Cl, Br or I in an amount within range of from 1.times.10.sup.-5 to 1.times.10.sup.-1 g.multidot.atm/mol of the host material.
    • PCT No.PCT / JP96 / 02149 Sec。 371日期:1998年7月20日 102(e)1998年7月20日PCT PCT 1996年7月30日PCT公布。 出版物WO97 / 27267 日期:1997年7月31日由m(Sr1-a,M1a)On(Mg1-b,M2b)O.2(Si1-c,Gec)O2:EuxLny表示的磷光体荧光体,其中M1为Ca和/或Ba,M2 Be,Zn和/或Cd,Ln是Sc,Y,La,Ce,Pr,Nd,Sm,Gd,Tb,Dy,Ho,Er,Tm,Yb,Lu,B,Al,Ga,In, Sb,Bi,As,P,Sn,Pb,Ti,Zr,Hf,V,Nb,Ta,Mo,W,Cr和/或Mn,其中a,b,c,m,n,x和y 在0≤a≤0.8的范围内,0≤b≤0.2,0≤c≤0.2,0.5≤m≤3.5,0.5≤n< = 1.5。 1×10-5×x = 1×10-1,1×10-5≤y≤1×10-1,并且其含有范围内的量的F,Cl,Br或I的卤素元素 从1×10-5至1×10-1gxatm / mol的主体材料。
    • 5. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREFOR
    • 半导体器件及其制造工艺
    • US20090267158A1
    • 2009-10-29
    • US12094755
    • 2006-11-21
    • Takashi Hase
    • Takashi Hase
    • H01L27/092H01L21/8238
    • H01L21/823842H01L21/28097H01L21/823871H01L29/4975H01L29/66545
    • There is provided a semiconductor device in which deviation in a work function is prevented by a gate electrode having a uniform composition and which has excellent operation properties by effectively controlling a Vth. The semiconductor device comprises an NMOS transistor and a PMOS transistor with a common line electrode, characterized in that the line electrode comprise an electrode section (A), an electrode section (B) and a diffusion barrier region formed in a part over an isolation region so that the electrode sections (A) and (B) are kept out of contact and the diffusion barrier region meets at least one of the following conditions (1) and (2). (1) The diffusion coefficient D1 in the above diffusion barrier region of the constituent element A′ of the above electrode section (A) is lower than the interdiffusion coefficient D2 of the constituent element A′ between electrode section (A) materials. (2) The diffusion coefficient D3 in the above diffusion barrier region of the constituent element B′ of the above electrode section (B) is lower than the interdiffusion coefficient D4 of the constituent element B′ between electrode section (B) materials.
    • 提供了一种半导体器件,通过有效地控制Vth,通过具有均匀组成的栅电极防止功函中的偏差,并且具有优异的操作特性。 半导体器件包括NMOS晶体管和具有公共线电极的PMOS晶体管,其特征在于,线电极包括电极部分(A),电极部分(B)和形成在隔离区域上的部分中的扩散阻挡区域 使得电极部分(A)和(B)保持不接触,并且扩散阻挡区域满足以下条件(1)和(2)中的至少一个。 (1)上述电极部(A)的构成元素A'的扩散阻挡区域的扩散系数D1低于电极部(A)材料之间的构成元素A'的相互扩散系数D2。 (2)上述电极部(B)的构成元件B'的扩散阻挡区域的扩散系数D3低于电极部(B)材料之间的构成元件B'的相互扩散系数D4。
    • 7. 发明授权
    • Method of producing a bismuth layer structured ferroelectric thin film
    • 生产铋层结构铁电薄膜的方法
    • US06194227B1
    • 2001-02-27
    • US09174393
    • 1998-10-14
    • Takashi Hase
    • Takashi Hase
    • H01L2100
    • H01L21/31691H01L28/56
    • The surface of a Si substrate is coated with a lower electrode of precious metal (Pt), then a buffer layer comprising an oxide thin film containing Bi is deposited. On the surface of the buffer layer, a thin film of a Bi layer structured ferroelectric substance is formed. Thus, reaction of the Bi layer structured ferroelectric substance with the precious metal coating the Si substrate is avoided during crystallization carried out at a low temperature. Therefore, deviation in composition of the thin film thus formed is suppressed to provide the thin film with a high density. When the thickness of the buffer layer is not greater than five percent of that of the Bi layer structured ferroelectric thin film, electrical characteristics of a capacitor are not deteriorated. When electrical connection is conducted by polycrystalline Si, production of oxide can be avoided by deposition at 650° C.
    • Si衬底的表面涂覆有贵金属(Pt)的下电极,然后沉积包含含有Bi的氧化物薄膜的缓冲层。 在缓冲层的表面形成有Bi层结构的铁电体的薄膜。 因此,在低温下进行结晶时避免了Bi层结构的铁电体与覆盖Si衬底的贵金属的反应。 因此,抑制如此形成的薄膜的组成偏差,从而提供高密度的薄膜。 当缓冲层的厚度不大于Bi层结构的铁电薄膜的厚度的5%时,电容器的电特性不会劣化。 当通过多晶硅进行电连接时,可以通过在650℃下沉积来避免生成氧化物。